Compare commits
No commits in common. 'c9' and 'c9-beta' have entirely different histories.
@ -1,93 +0,0 @@
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commit 73d8177ce0d2fcb7693cacee4778d0845ebd3788
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Author: sathya priya kumar <SathyaPriya.K@amd.com>
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Date: Thu Jun 13 05:29:09 2024 +0000
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rasdaemon: mce-amd-smca: Optimizing decoding of MCA_CTL_SMU bits
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Optimize smca_smu2_mce_desc in better way from the commit ced615c.
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Update existing array with extended error descriptions instead
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of creating new array, simplifying the code.
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Signed-off-by: Sathya Priya Kumar <sathyapriya.k@amd.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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---
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mce-amd-smca.c | 29 +++--------------------------
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ras-mce-handler.h | 1 -
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2 files changed, 3 insertions(+), 27 deletions(-)
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--- rasdaemon-0.6.7.orig/mce-amd-smca.c 2024-07-18 11:14:26.008582740 -0400
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+++ rasdaemon-0.6.7/mce-amd-smca.c 2024-07-18 11:15:05.510270132 -0400
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@@ -397,7 +397,7 @@ static const char * const smca_smu_mce_d
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"An ECC or parity error in an SMU RAM instance",
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};
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-static const char * smca_smu2_mce_desc[64] = {
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+static const char * const smca_smu2_mce_desc[] = {
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"High SRAM ECC or parity error",
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"Low SRAM ECC or parity error",
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"Data Cache Bank A ECC or parity error",
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@@ -410,14 +410,13 @@ static const char * smca_smu2_mce_desc[6
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"Instruction Tag Cache Bank B ECC or parity error",
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"System Hub Read Buffer ECC or parity error",
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"PHY RAS ECC Error",
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-};
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-
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-static const char * smca_smu2_ext_mce_desc[] = {
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+ [12 ... 57] = "Reserved",
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"A correctable error from a GFX Sub-IP",
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"A fatal error from a GFX Sub-IP",
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"Reserved",
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"Reserved",
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"A poison error from a GFX Sub-IP",
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+ "Reserved",
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};
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static const char * const smca_mp5_mce_desc[] = {
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@@ -824,27 +823,6 @@ static struct smca_bank_name smca_names[
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[SMCA_GMI_PHY] = { "Global Memory Interconnect PHY Unit" },
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};
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-void smca_smu2_ext_err_desc(void)
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-{
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- int i, j;
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- int smu2_bits = 62;
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-
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- /*
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- * MCA_CTL_SMU error stings are defined for b'58:59 and b'62
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- * in MI300A AMD systems. See AMD PPR MCA::SMU::MCA_CTL_SMU
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- *
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- * b'0:11 can be decoded from existing array smca_smu2_mce_desc.
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- * b'12:57 are Reserved and b'58:62 are appended to the
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- * smca_smu2_mce_desc.
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- */
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- for (i = 12, j = 0; i < smu2_bits || j < 5; i++, j++) {
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- for ( ; i < 58; i++)
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- smca_smu2_mce_desc[i] = "Reserved";
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-
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- smca_smu2_mce_desc[i] = smca_smu2_ext_mce_desc[j];
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- }
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-}
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-
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void amd_decode_errcode(struct mce_event *e)
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{
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@@ -936,7 +914,6 @@ unsigned short xec = (e->status >> 16) &
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mcatype_hwid = HWID_MCATYPE(ipid_high & MCI_IPID_HWID,
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(ipid_high & MCI_IPID_MCATYPE) >> 16);
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- smca_smu2_ext_err_desc();
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fixup_hwid(m, &mcatype_hwid);
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for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
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--- rasdaemon-0.6.7.orig/ras-mce-handler.h 2024-07-18 11:14:26.008582740 -0400
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+++ rasdaemon-0.6.7/ras-mce-handler.h 2024-07-18 11:14:28.987559165 -0400
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@@ -121,7 +121,6 @@ int set_intel_imc_log(enum cputype cputy
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/* Undertake AMD SMCA Error Decoding */
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void decode_smca_error(struct mce_event *e, struct mce_priv *m);
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void amd_decode_errcode(struct mce_event *e);
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-void smca_smu2_ext_err_desc(void);
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/* Per-CPU-type decoders for Intel CPUs */
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void p4_decode_model(struct mce_event *e);
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@ -1,34 +0,0 @@
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commit 7ed2da7aedf8bc8ad4c4efe7acbda60ba061be6e
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Author: Aristeu Rozanski <arozansk@redhat.com>
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Date: Tue Apr 9 10:06:30 2024 -0400
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mce-amd-smca: update smca_hwid to use smca_bank_types
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bank_type is used as smca_bank_types everywhere, there's no point in
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declaring it as unsigned int. It also upsets covscan:
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3. rasdaemon-0.6.7/mce-amd-smca.c:914: assignment: Assigning: "bank_type" = "s_hwid->bank_type".
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7. rasdaemon-0.6.7/mce-amd-smca.c:926: cond_at_most: Checking "bank_type >= 64U" implies that "bank_type" and "s_hwid->bank_type" may be up to 63 on the false branch.
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14. rasdaemon-0.6.7/mce-amd-smca.c:942: overrun-local: Overrunning array "smca_mce_descs" of 38 16-byte elements at element index 63 (byte offset 1023) using index "bank_type" (which evaluates to 63).
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# 940| /* Only print the descriptor of valid extended error code */
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# 941| if (xec < smca_mce_descs[bank_type].num_descs)
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# 942|-> mce_snprintf(e->mcastatus_msg,
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# 943| "%s. Ext Err Code: %d",
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# 944| smca_mce_descs[bank_type].descs[xec],
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Signed-off-by: Aristeu Rozanski <arozansk@redhat.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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diff --git a/mce-amd-smca.c b/mce-amd-smca.c
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index 7521ff7..6632663 100644
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--- a/mce-amd-smca.c
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+++ b/mce-amd-smca.c
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@@ -706,7 +706,7 @@ static struct smca_mce_desc smca_mce_descs[] = {
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};
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struct smca_hwid {
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- unsigned int bank_type; /* Use with smca_bank_types for easy indexing.*/
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+ enum smca_bank_types bank_type;
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uint32_t mcatype_hwid; /* mcatype,hwid bit 63-32 in MCx_IPID Register*/
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};
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@ -1,22 +0,0 @@
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commit 885e546add918457c453bd3f753ac7df90b39e36
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Author: weidongkl <weidongkl@sina.com>
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Date: Tue Sep 19 16:29:21 2023 +0800
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Add a space between "diskerror_event" and "store"
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Signed-off-by: weidongkl <weidongkl@sina.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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diff --git a/ras-record.c b/ras-record.c
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index a5f99ae..6b050bb 100644
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--- a/ras-record.c
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+++ b/ras-record.c
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@@ -484,7 +484,7 @@ int ras_store_diskerror_event(struct ras_events *ras, struct diskerror_event *ev
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if (!priv || !priv->stmt_diskerror_event)
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return 0;
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- log(TERM, LOG_INFO, "diskerror_eventstore: %p\n", priv->stmt_diskerror_event);
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+ log(TERM, LOG_INFO, "diskerror_event store: %p\n", priv->stmt_diskerror_event);
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sqlite3_bind_text(priv->stmt_diskerror_event, 1, ev->timestamp, -1, NULL);
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sqlite3_bind_text(priv->stmt_diskerror_event, 2, ev->dev, -1, NULL);
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@ -1,24 +0,0 @@
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commit 9bd84aef87978b806178a73ed33c39d6c442fc1f
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Author: weidong <weidongkl@sina.com>
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Date: Tue Aug 8 08:59:12 2023 +0000
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add ':' before error output
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All prints except disk are preceded by a colon
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Signed-off-by: weidong <weidongkl@sina.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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diff --git a/util/ras-mc-ctl.in b/util/ras-mc-ctl.in
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index dc326d3..13078c2 100755
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--- a/util/ras-mc-ctl.in
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+++ b/util/ras-mc-ctl.in
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@@ -1469,7 +1469,7 @@ sub errors
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$out .= "\n";
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}
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if ($out ne "") {
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- print "Disk errors\n$out\n";
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+ print "Disk errors:\n$out\n";
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} else {
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print "No disk errors.\n\n";
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}
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@ -1,117 +0,0 @@
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commit 9c86f6255f67a8bae28cd46c54500fc16bfc7a30
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Author: Yang Shi <shy828301@gmail.com>
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Date: Mon Apr 4 16:34:05 2022 -0700
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rasdaemon: use the new block_rq_error tracepoint
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Since Linux 5.18-rc1 a new block tracepoint called block_rq_error is
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available for tracing disk error events dedicatedly. Currently
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rasdaemon is using block_rq_complete which also traces successful cases.
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It incurs excessive tracing logs and somehow overhead since the event is
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triggered quite often.
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Use the new tracepoint for disk error reporting, and the new trace point
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has the same format as block_rq_complete.
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Signed-off-by: Yang Shi <shy828301@gmail.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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---
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ras-events.c | 53 ++++++++++-------------------------------------------
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ras-record.c | 2 +-
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2 files changed, 11 insertions(+), 44 deletions(-)
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--- rasdaemon-0.6.7.orig/ras-events.c 2024-05-14 11:05:40.020599541 -0400
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+++ rasdaemon-0.6.7/ras-events.c 2024-05-14 11:06:38.831067957 -0400
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@@ -27,6 +27,7 @@ * Foundation, Inc., 51 Franklin Street,
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#include <sys/poll.h>
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#include <signal.h>
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#include <sys/signalfd.h>
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+#include <linux/version.h>
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#include "libtrace/kbuffer.h"
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#include "libtrace/event-parse.h"
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#include "ras-mc-handler.h"
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@@ -229,7 +230,7 @@ if (rc < 0) {
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#endif
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#ifdef HAVE_DISKERROR
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- rc |= __toggle_ras_mc_event(ras, "block", "block_rq_complete", enable);
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+ rc |= __toggle_ras_mc_event(ras, "block", "block_rq_error", enable);
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#endif
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#ifdef HAVE_MEMORY_FAILURE
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@@ -241,37 +242,6 @@ free_ras:
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return rc;
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}
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-/*
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- * Set kernel filter. libtrace doesn't provide an API for setting filters
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- * in kernel, we have to implement it here.
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- */
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-static int filter_ras_mc_event(struct ras_events *ras, char *group, char *event,
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- const char *filter_str)
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-{
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- int fd, rc;
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- char fname[MAX_PATH + 1];
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-
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- snprintf(fname, sizeof(fname), "events/%s/%s/filter", group, event);
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- fd = open_trace(ras, fname, O_RDWR | O_APPEND);
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- if (fd < 0) {
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- log(ALL, LOG_WARNING, "Can't open filter file\n");
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- return errno;
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- }
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-
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- rc = write(fd, filter_str ,strlen(filter_str));
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- if (rc < 0) {
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- log(ALL, LOG_WARNING, "Can't write to filter file\n");
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- close(fd);
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- return rc;
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- }
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- close(fd);
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- if (!rc) {
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- log(ALL, LOG_WARNING, "Nothing was written on filter file\n");
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- return EIO;
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- }
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-
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- return 0;
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-}
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/*
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* Tracing read code
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@@ -901,17 +871,14 @@ (void)open("/sys/kernel/debug/ras/daemon
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#endif
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#ifdef HAVE_DISKERROR
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- rc = filter_ras_mc_event(ras, "block", "block_rq_complete", "error != 0");
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- if (!rc) {
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- rc = add_event_handler(ras, pevent, page_size, "block",
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- "block_rq_complete", ras_diskerror_event_handler,
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- NULL, DISKERROR_EVENT);
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- if (!rc)
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- num_events++;
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- else
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- log(ALL, LOG_ERR, "Can't get traces from %s:%s\n",
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- "block", "block_rq_complete");
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- }
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+ rc = add_event_handler(ras, pevent, page_size, "block",
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+ "block_rq_error", ras_diskerror_event_handler,
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+ NULL, DISKERROR_EVENT);
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+ if (!rc)
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+ num_events++;
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+ else
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+ log(ALL, LOG_ERR, "Can't get traces from %s:%s\n",
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+ "block", "block_rq_error");
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|
||||||
#endif
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||||||
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|
||||||
#ifdef HAVE_MEMORY_FAILURE
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||||||
--- rasdaemon-0.6.7.orig/ras-record.c 2024-05-14 11:07:24.573654494 -0400
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||||||
+++ rasdaemon-0.6.7/ras-record.c 2024-05-14 11:07:07.626807674 -0400
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@@ -456,7 +456,7 @@ return 0;
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||||||
#endif
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||||||
/*
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|
||||||
- * Table and functions to handle block:block_rq_complete
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||||||
+ * Table and functions to handle block:block_rq_error
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||||||
*/
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|
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#ifdef HAVE_DISKERROR
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@ -1,94 +0,0 @@
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commit ced615cf8146f51b5d6fe7a29107a2adc77407ca
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|
||||||
Author: Sathya Priya Kumar <sathyapriya.k@amd.com>
|
|
||||||
Date: Thu Jan 11 01:20:07 2024 -0600
|
|
||||||
|
|
||||||
rasdaemon: Add error decoding for MCA_CTL_SMU extended bits
|
|
||||||
|
|
||||||
Enable error decoding support for the newly added extended
|
|
||||||
error bit descriptions from MCA_CTL_SMU.
|
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||||||
b'0:11 can be decoded from existing array smca_smu2_mce_desc.
|
|
||||||
Define a function to append the newly defined b'58:62 to the
|
|
||||||
smca_smu2_mce_desc. This reduces the maintaining Reserved bits
|
|
||||||
from b'12:57 in the code.
|
|
||||||
|
|
||||||
Signed-off-by: Sathya Priya Kumar <sathyapriya.k@amd.com>
|
|
||||||
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
|
|
||||||
|
|
||||||
---
|
|
||||||
mce-amd-smca.c | 33 ++++++++++++++++++++++++++++++++-
|
|
||||||
ras-mce-handler.h | 1 +
|
|
||||||
2 files changed, 33 insertions(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- rasdaemon-0.6.7.orig/mce-amd-smca.c 2024-06-28 10:34:16.453522865 -0400
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|
||||||
+++ rasdaemon-0.6.7/mce-amd-smca.c 2024-06-28 10:34:46.049124270 -0400
|
|
||||||
@@ -397,7 +397,7 @@ static const char * const smca_smu_mce_d
|
|
||||||
"An ECC or parity error in an SMU RAM instance",
|
|
||||||
};
|
|
||||||
|
|
||||||
-static const char * const smca_smu2_mce_desc[] = {
|
|
||||||
+static const char * smca_smu2_mce_desc[64] = {
|
|
||||||
"High SRAM ECC or parity error",
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"Low SRAM ECC or parity error",
|
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||||||
"Data Cache Bank A ECC or parity error",
|
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@@ -409,6 +409,15 @@ static const char * const smca_smu2_mce_
|
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"Instruction Tag Cache Bank A ECC or parity error",
|
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||||||
"Instruction Tag Cache Bank B ECC or parity error",
|
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"System Hub Read Buffer ECC or parity error",
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+ "PHY RAS ECC Error",
|
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||||||
+};
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||||||
+
|
|
||||||
+static const char * smca_smu2_ext_mce_desc[] = {
|
|
||||||
+ "A correctable error from a GFX Sub-IP",
|
|
||||||
+ "A fatal error from a GFX Sub-IP",
|
|
||||||
+ "Reserved",
|
|
||||||
+ "Reserved",
|
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||||||
+ "A poison error from a GFX Sub-IP",
|
|
||||||
};
|
|
||||||
|
|
||||||
static const char * const smca_mp5_mce_desc[] = {
|
|
||||||
@@ -815,6 +824,27 @@ static struct smca_bank_name smca_names[
|
|
||||||
[SMCA_GMI_PHY] = { "Global Memory Interconnect PHY Unit" },
|
|
||||||
};
|
|
||||||
|
|
||||||
+void smca_smu2_ext_err_desc(void)
|
|
||||||
+{
|
|
||||||
+ int i, j;
|
|
||||||
+ int smu2_bits = 62;
|
|
||||||
+
|
|
||||||
+ /*
|
|
||||||
+ * MCA_CTL_SMU error stings are defined for b'58:59 and b'62
|
|
||||||
+ * in MI300A AMD systems. See AMD PPR MCA::SMU::MCA_CTL_SMU
|
|
||||||
+ *
|
|
||||||
+ * b'0:11 can be decoded from existing array smca_smu2_mce_desc.
|
|
||||||
+ * b'12:57 are Reserved and b'58:62 are appended to the
|
|
||||||
+ * smca_smu2_mce_desc.
|
|
||||||
+ */
|
|
||||||
+ for (i = 12, j = 0; i < smu2_bits || j < 5; i++, j++) {
|
|
||||||
+ for ( ; i < 58; i++)
|
|
||||||
+ smca_smu2_mce_desc[i] = "Reserved";
|
|
||||||
+
|
|
||||||
+ smca_smu2_mce_desc[i] = smca_smu2_ext_mce_desc[j];
|
|
||||||
+ }
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
void amd_decode_errcode(struct mce_event *e)
|
|
||||||
{
|
|
||||||
|
|
||||||
@@ -906,6 +936,7 @@ unsigned short xec = (e->status >> 16) &
|
|
||||||
mcatype_hwid = HWID_MCATYPE(ipid_high & MCI_IPID_HWID,
|
|
||||||
(ipid_high & MCI_IPID_MCATYPE) >> 16);
|
|
||||||
|
|
||||||
+ smca_smu2_ext_err_desc();
|
|
||||||
fixup_hwid(m, &mcatype_hwid);
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
|
|
||||||
--- rasdaemon-0.6.7.orig/ras-mce-handler.h 2024-06-28 10:34:16.453522865 -0400
|
|
||||||
+++ rasdaemon-0.6.7/ras-mce-handler.h 2024-06-28 10:34:17.795508302 -0400
|
|
||||||
@@ -121,6 +121,7 @@ int set_intel_imc_log(enum cputype cputy
|
|
||||||
/* Undertake AMD SMCA Error Decoding */
|
|
||||||
void decode_smca_error(struct mce_event *e, struct mce_priv *m);
|
|
||||||
void amd_decode_errcode(struct mce_event *e);
|
|
||||||
+void smca_smu2_ext_err_desc(void);
|
|
||||||
|
|
||||||
/* Per-CPU-type decoders for Intel CPUs */
|
|
||||||
void p4_decode_model(struct mce_event *e);
|
|
||||||
Loading…
Reference in new issue