Jens Petersen
13 years ago
parent
a27c47f9d9
commit
6b98066a85
@ -1,29 +0,0 @@
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From 1cbf3bcae87dd102942d85ce71ea17d42d4b5f5a Mon Sep 17 00:00:00 2001
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From: Karel Gardas <karel.gardas@centrum.cz>
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Date: Tue, 14 Feb 2012 08:03:07 +0100
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Subject: [PATCH 2/2] fix ARM StgCRun to not save and restore r11/fp register twice
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---
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rts/StgCRun.c | 4 ++--
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1 files changed, 2 insertions(+), 2 deletions(-)
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--- a/rts/StgCRun.c
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+++ b/rts/StgCRun.c
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@@ -632,7 +632,7 @@
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/*
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* save callee-saves registers on behalf of the STG code.
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*/
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- "stmfd sp!, {r4-r11, fp, ip, lr}\n\t"
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+ "stmfd sp!, {r4-r10, fp, ip, lr}\n\t"
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#if !defined(arm_HOST_ARCH_PRE_ARMv6)
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"vstmdb sp!, {d8-d11}\n\t"
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#endif
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@@ -669,7 +669,7 @@
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#if !defined(arm_HOST_ARCH_PRE_ARMv6)
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"vldmia sp!, {d8-d11}\n\t"
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#endif
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- "ldmfd sp!, {r4-r11, fp, ip, lr}\n\t"
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+ "ldmfd sp!, {r4-r10, fp, ip, lr}\n\t"
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: "=r" (r)
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: "r" (f), "r" (basereg), "i" (RESERVED_C_STACK_BYTES)
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#if !defined(__thumb__)
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@ -1,34 +0,0 @@
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From 957f778cb971d63cbbea0c71c727c94474b1b905 Mon Sep 17 00:00:00 2001
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From: Karel Gardas <karel.gardas@centrum.cz>
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Date: Tue, 14 Feb 2012 08:01:47 +0100
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Subject: [PATCH 1/2] fix ARM's StgCRun clobbered register list for both ARM and Thumb modes
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---
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rts/StgCRun.c | 16 +++++++++++++++-
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1 files changed, 15 insertions(+), 1 deletions(-)
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--- a/rts/StgCRun.c
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+++ b/rts/StgCRun.c
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@@ -672,7 +672,21 @@
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"ldmfd sp!, {r4-r11, fp, ip, lr}\n\t"
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: "=r" (r)
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: "r" (f), "r" (basereg), "i" (RESERVED_C_STACK_BYTES)
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- : "%r4", "%r5", "%r6", "%r8", "%r9", "%r10", "%r11", "%fp", "%ip", "%lr"
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+#if !defined(__thumb__)
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+ /* In ARM mode, r11/fp is frame-pointer and so we cannot mark
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+ it as clobbered. If we do so, GCC complains with error. */
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+ : "%r4", "%r5", "%r6", "%r7", "%r8", "%r9", "%r10", "%ip", "%lr"
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+#else
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+ /* In Thumb mode r7 is frame-pointer and so we cannot mark it
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+ as clobbered. On the other hand we mark as clobbered also
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+ those regs not used in Thumb mode. Hard to judge if this is
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+ needed, but certainly Haskell code is using them for
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+ placing GHC's virtual registers there. See
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+ includes/stg/MachRegs.h Please note that Haskell code is
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+ compiled by GHC/LLVM into ARM code (not Thumb!), at least
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+ as of February 2012 */
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+ : "%r4", "%r5", "%r6", "%r8", "%r9", "%r10", "%fp", "%ip", "%lr"
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+#endif
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);
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return r;
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}
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File diff suppressed because it is too large
Load Diff
@ -1,16 +0,0 @@
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Description: Use VFPv3-D16 FPU for ARM builds
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Author: Jani Monoses <jani@ubuntu.com>
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Index: ghc/aclocal.m4
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===================================================================
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--- ghc.orig/aclocal.m4 2012-02-01 18:10:32.000000000 +0000
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+++ ghc/aclocal.m4 2012-03-10 16:40:32.415005650 +0000
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@@ -333,7 +333,7 @@
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],
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[changequote(, )dnl
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ARM_ISA=ARMv7
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- ARM_ISA_EXT="[VFPv3,NEON]"
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+ ARM_ISA_EXT="[VFPv3D16,NEON]"
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changequote([, ])dnl
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])
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])
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@ -1,26 +0,0 @@
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Description: If we are on armhf, tell llvm to generate code for this ABI. Not
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forwarded upstream, because they will do a more 'proper' patch. See upstream
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bug #5914.
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Author: Iain Lane <laney@debian.org>
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Index: ghc/compiler/main/DriverPipeline.hs
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===================================================================
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--- ghc.orig/compiler/main/DriverPipeline.hs 2012-03-10 16:41:46.000000000 +0000
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+++ ghc/compiler/main/DriverPipeline.hs 2012-03-10 16:42:59.209169474 +0000
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@@ -1,5 +1,5 @@
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{-# OPTIONS -fno-cse #-}
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-{-# LANGUAGE NamedFieldPuns #-}
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+{-# LANGUAGE NamedFieldPuns, CPP #-}
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-- -fno-cse is needed for GLOBAL_VAR's to behave properly
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-----------------------------------------------------------------------------
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@@ -1379,6 +1379,9 @@
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then ["-mattr=+v7,+vfp3"]
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else if (elem VFPv3D16 ext)
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then ["-mattr=+v7,+vfp3,+d16"]
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+#ifdef __ARM_PCS_VFP
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+ ++ ["-float-abi=hard"]
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+#endif
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else []
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_ -> []
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