From 92e249d285da7a277cdb2f9455ff92644a1b0118 Mon Sep 17 00:00:00 2001 From: MSVSphere Packaging Team Date: Wed, 3 Apr 2024 18:32:07 +0300 Subject: [PATCH] import seabios-1.16.0-4.module+el8.9.0+19570+14a90618 --- .gitignore | 1 + .seabios.metadata | 1 + SOURCES/0002-allow-1TB-of-RAM.patch | 71 +++ ...vendor-version-fields-to-Seabios-0.5.patch | 50 ++ ...around-for-a-win8.1-32-S4-resume-bug.patch | 67 +++ SOURCES/config.seabios-128k | 20 + SOURCES/config.seabios-256k | 3 + SOURCES/config.vga.bochs-display | 3 + SOURCES/config.vga.cirrus | 3 + SOURCES/config.vga.qxl | 6 + SOURCES/config.vga.ramfb | 3 + SOURCES/config.vga.stdvga | 3 + SOURCES/config.vga.virtio | 6 + ...-ZoneHigh-when-there-is-enough-memor.patch | 72 +++ ...alloc-use-variable-for-ZoneHigh-size.patch | 71 +++ ...i-refactor-the-pci_config_-functions.patch | 174 +++++++ ...ce-standard-PCI-configuration-access.patch | 159 +++++++ ...t-skip-unbootable-disks-optimitation.patch | 40 ++ ...-blk-use-larger-default-request-size.patch | 42 ++ SPECS/seabios.spec | 441 ++++++++++++++++++ 20 files changed, 1236 insertions(+) create mode 100644 .gitignore create mode 100644 .seabios.metadata create mode 100644 SOURCES/0002-allow-1TB-of-RAM.patch create mode 100644 SOURCES/0003-smbios-set-bios-vendor-version-fields-to-Seabios-0.5.patch create mode 100644 SOURCES/0004-Workaround-for-a-win8.1-32-S4-resume-bug.patch create mode 100644 SOURCES/config.seabios-128k create mode 100644 SOURCES/config.seabios-256k create mode 100644 SOURCES/config.vga.bochs-display create mode 100644 SOURCES/config.vga.cirrus create mode 100644 SOURCES/config.vga.qxl create mode 100644 SOURCES/config.vga.ramfb create mode 100644 SOURCES/config.vga.stdvga create mode 100644 SOURCES/config.vga.virtio create mode 100644 SOURCES/seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch create mode 100644 SOURCES/seabios-malloc-use-variable-for-ZoneHigh-size.patch create mode 100644 SOURCES/seabios-pci-refactor-the-pci_config_-functions.patch create mode 100644 SOURCES/seabios-reset-force-standard-PCI-configuration-access.patch create mode 100644 SOURCES/seabios-shortcut-skip-unbootable-disks-optimitation.patch create mode 100644 SOURCES/seabios-virtio-blk-use-larger-default-request-size.patch create mode 100644 SPECS/seabios.spec diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..fa2b595 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +SOURCES/seabios-1.16.0.tar.gz diff --git a/.seabios.metadata b/.seabios.metadata new file mode 100644 index 0000000..41a6710 --- /dev/null +++ b/.seabios.metadata @@ -0,0 +1 @@ +0cc6b21cfbafa1f9f158c9aca1ab9f5174ebede2 SOURCES/seabios-1.16.0.tar.gz diff --git a/SOURCES/0002-allow-1TB-of-RAM.patch b/SOURCES/0002-allow-1TB-of-RAM.patch new file mode 100644 index 0000000..979e2ba --- /dev/null +++ b/SOURCES/0002-allow-1TB-of-RAM.patch @@ -0,0 +1,71 @@ +From d659d62b9c094acea66f6f7506877f210a9dd182 Mon Sep 17 00:00:00 2001 +From: Andrea Arcangeli +Date: Tue, 8 Oct 2013 17:07:23 +0200 +Subject: allow >1TB of RAM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Andrea Arcangeli +Message-id: <1381252043-13480-2-git-send-email-aarcange@redhat.com> +Patchwork-id: 54785 +O-Subject: [RHEL-7.0 seabios PATCH] allow >1TB of RAM +Bugzilla: 1016974 +RH-Acked-by: Paolo Bonzini +RH-Acked-by: Gleb Natapov +RH-Acked-by: Laszlo Ersek + +Receive bits 40-48 from qemu to setup e820 maps with more than 1TB of ram. + +Signed-off-by: Andrea Arcangeli +--- + src/cmos.h | 7 ++++--- + src/post.c | 7 ++++--- + 2 files changed, 8 insertions(+), 6 deletions(-) + +(cherry picked from commit 0dea1df1f9b9a64bd9e71dd1a7b4c6cc9962afa0) +Signed-off-by: Paweł Poławski +--- + src/fw/paravirt.c | 7 ++++--- + src/hw/rtc.h | 7 ++++--- + 2 files changed, 8 insertions(+), 6 deletions(-) + +diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c +index fba4e52d..090d6555 100644 +--- a/src/fw/paravirt.c ++++ b/src/fw/paravirt.c +@@ -516,9 +516,10 @@ qemu_cfg_e820(void) + } + + // Check for memory over 4Gig in cmos +- u64 high = ((rtc_read(CMOS_MEM_HIGHMEM_LOW) << 16) +- | ((u32)rtc_read(CMOS_MEM_HIGHMEM_MID) << 24) +- | ((u64)rtc_read(CMOS_MEM_HIGHMEM_HIGH) << 32)); ++ u64 high = ((rtc_read(CMOS_MEM_HIGHMEM_16) << 16) ++ | ((u32)rtc_read(CMOS_MEM_HIGHMEM_24) << 24) ++ | ((u64)rtc_read(CMOS_MEM_HIGHMEM_32) << 32) ++ | ((u64)rtc_read(CMOS_MEM_HIGHMEM_40) << 40)); + RamSizeOver4G = high; + e820_add(0x100000000ull, high, E820_RAM); + dprintf(1, "RamSizeOver4G: 0x%016llx [cmos]\n", RamSizeOver4G); +diff --git a/src/hw/rtc.h b/src/hw/rtc.h +index 252e73a4..c4369f81 100644 +--- a/src/hw/rtc.h ++++ b/src/hw/rtc.h +@@ -41,9 +41,10 @@ + #define CMOS_BIOS_BOOTFLAG1 0x38 + #define CMOS_BIOS_DISKTRANSFLAG 0x39 + #define CMOS_BIOS_BOOTFLAG2 0x3d +-#define CMOS_MEM_HIGHMEM_LOW 0x5b +-#define CMOS_MEM_HIGHMEM_MID 0x5c +-#define CMOS_MEM_HIGHMEM_HIGH 0x5d ++#define CMOS_MEM_HIGHMEM_16 0x5b ++#define CMOS_MEM_HIGHMEM_24 0x5c ++#define CMOS_MEM_HIGHMEM_32 0x5d ++#define CMOS_MEM_HIGHMEM_40 0x5e + #define CMOS_BIOS_SMP_COUNT 0x5f + + // RTC register flags +-- +2.31.1 + diff --git a/SOURCES/0003-smbios-set-bios-vendor-version-fields-to-Seabios-0.5.patch b/SOURCES/0003-smbios-set-bios-vendor-version-fields-to-Seabios-0.5.patch new file mode 100644 index 0000000..081cd84 --- /dev/null +++ b/SOURCES/0003-smbios-set-bios-vendor-version-fields-to-Seabios-0.5.patch @@ -0,0 +1,50 @@ +From daf5bb8573c22dc133b4f7a8a07a174dbb30a2c5 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann +Date: Mon, 28 Jul 2014 12:14:11 +0200 +Subject: smbios: set bios vendor/version fields to Seabios/0.5.1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Message-id: <1406549651-26021-2-git-send-email-kraxel@redhat.com> +Patchwork-id: 60264 +O-Subject: [RHEL-7.1 seabios PATCH 1/1] smbios: set bios vendor/version fields to Seabios/0.5.1 +Bugzilla: 1123299 +RH-Acked-by: Miroslav Rezanina +RH-Acked-by: Laszlo Ersek +RH-Acked-by: Paolo Bonzini + +Mimic rhel6/seabios commit 1389643dad35a63362cd7d8357693f01175ef473. +Affects all 6.x and 7.0 machine types. + +Note: 7.1+ machine types will switch over to the new-style smbios +handling in qemu 2.1 + seabios 1.7.5 (and ovmf), where seabios will +fill in the actual version information instead of the bogous 0.5.1 +which we are using here for backward compatibility reasons. + +Signed-off-by: Gerd Hoffmann + +(cherry picked from commit cc21704fcfbc62af6789e1362eb05a2dc2b56cbf) +Signed-off-by: Paweł Poławski +--- + src/fw/smbios.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/fw/smbios.c b/src/fw/smbios.c +index 730b6898..cb6fc03f 100644 +--- a/src/fw/smbios.c ++++ b/src/fw/smbios.c +@@ -174,8 +174,8 @@ smbios_init_type_0(void *start) + p->header.length = sizeof(struct smbios_type_0); + p->header.handle = 0; + +- load_str_field_with_default(0, vendor_str, BUILD_APPNAME); +- load_str_field_with_default(0, bios_version_str, BUILD_APPNAME); ++ load_str_field_with_default(0, vendor_str, "Seabios"); ++ load_str_field_with_default(0, bios_version_str, "0.5.1"); + + p->bios_starting_address_segment = 0xe800; + +-- +2.31.1 + diff --git a/SOURCES/0004-Workaround-for-a-win8.1-32-S4-resume-bug.patch b/SOURCES/0004-Workaround-for-a-win8.1-32-S4-resume-bug.patch new file mode 100644 index 0000000..9651e10 --- /dev/null +++ b/SOURCES/0004-Workaround-for-a-win8.1-32-S4-resume-bug.patch @@ -0,0 +1,67 @@ +From 0182f348c6bc7cb676cb52941cbb0b220639c4e0 Mon Sep 17 00:00:00 2001 +From: Radim Krcmar +Date: Mon, 10 Mar 2014 15:14:27 +0100 +Subject: Workaround for a win8.1-32 S4 resume bug +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Radim Krcmar +Message-id: <1394464467-23560-1-git-send-email-rkrcmar@redhat.com> +Patchwork-id: 58069 +O-Subject: [RHEL7.0 seabios PATCH] Workaround for a win8.1-32 S4 resume bug +Bugzilla: 1050775 +RH-Acked-by: Paolo Bonzini +RH-Acked-by: Gerd Hoffmann +RH-Acked-by: Laszlo Ersek + +bug: https://bugzilla.redhat.com/show_bug.cgi?id=1050775 +brew: http://brewweb.devel.redhat.com/brew/taskinfo?taskID=7176174 +This patch has no upstream equivalent. + +When a 32 bit version of windows 8.1 resumes from suspend, it writes 1 +into 0x72 in the early boot because it didn't expect a NULL pointer. +0x72 is lower offset byte of 0x1c interrupt entry, so we jump into a +middle of other function if this interrupt is triggered. + +Because 0x1c is only triggered from our handle_08, we detect if our +default value (function that does only iret) has its lower offset byte +overwritten and skip it in that case. +(Windows never sets own callback there, so we always detect this bug + correctly, as seabios doesn't use it either + Other sources shouldn't incorrectly overwrite it or use seabios code, + but it is quite ok even if the guest did this on purpose.) + +The reason Windows uses NULL pointer is still unknown, but this bug is +blocking WHQL certification, so we have to work around it in 7.0. + +Signed-off-by: Radim Krčmář + +(cherry picked from commit 8629f200084ce1aab31d193280d34b5fb16e543f) +Signed-off-by: Paweł Poławski +--- + src/clock.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/src/clock.c b/src/clock.c +index e44e1120..298a7229 100644 +--- a/src/clock.c ++++ b/src/clock.c +@@ -309,7 +309,13 @@ handle_08(void) + struct bregs br; + memset(&br, 0, sizeof(br)); + br.flags = F_IF; +- call16_int(0x1c, &br); ++ struct segoff_s isr1c = GET_IVT(0x1c); ++ // hardcoded address of entry_iret_official with lower segment byte ++ // overwritten by 1 ++ if (isr1c.seg == ((SEG_BIOS & ~0xff) | 0x1) && isr1c.offset == 0xff53) ++ dprintf(1, "Worked around win8.1-32 S4 resume bug\n"); ++ else ++ call16_int(0x1c, &br); + + pic_eoi1(); + } +-- +2.31.1 + diff --git a/SOURCES/config.seabios-128k b/SOURCES/config.seabios-128k new file mode 100644 index 0000000..d8948a4 --- /dev/null +++ b/SOURCES/config.seabios-128k @@ -0,0 +1,20 @@ +CONFIG_XEN=n +CONFIG_ESP_SCSI=n +CONFIG_LSI_SCSI=n +CONFIG_USB_OHCI=n +CONFIG_BOOTSPLASH=n +CONFIG_MEGASAS=n +CONFIG_PVSCSI=n +CONFIG_ROM_SIZE=128 +CONFIG_USB_OHCI=n +CONFIG_USB_XHCI=n +CONFIG_USB_UAS=n +CONFIG_TCGBIOS=n +CONFIG_USE_SMM=n +CONFIG_NVME=n +CONFIG_VGAHOOKS=n +CONFIG_NVME=n +CONFIG_VGAHOOKS=n +CONFIG_SERCON=n +CONFIG_SDCARD=n +CONFIG_MPT_SCSI=n diff --git a/SOURCES/config.seabios-256k b/SOURCES/config.seabios-256k new file mode 100644 index 0000000..65e5015 --- /dev/null +++ b/SOURCES/config.seabios-256k @@ -0,0 +1,3 @@ +# for qemu machine types 2.0 + newer +CONFIG_QEMU=y +CONFIG_ROM_SIZE=256 diff --git a/SOURCES/config.vga.bochs-display b/SOURCES/config.vga.bochs-display new file mode 100644 index 0000000..d2adaae --- /dev/null +++ b/SOURCES/config.vga.bochs-display @@ -0,0 +1,3 @@ +CONFIG_BUILD_VGABIOS=y +CONFIG_DISPLAY_BOCHS=y +CONFIG_VGA_PCI=y diff --git a/SOURCES/config.vga.cirrus b/SOURCES/config.vga.cirrus new file mode 100644 index 0000000..c8fe582 --- /dev/null +++ b/SOURCES/config.vga.cirrus @@ -0,0 +1,3 @@ +CONFIG_BUILD_VGABIOS=y +CONFIG_VGA_CIRRUS=y +CONFIG_VGA_PCI=y diff --git a/SOURCES/config.vga.qxl b/SOURCES/config.vga.qxl new file mode 100644 index 0000000..d393f0c --- /dev/null +++ b/SOURCES/config.vga.qxl @@ -0,0 +1,6 @@ +CONFIG_BUILD_VGABIOS=y +CONFIG_VGA_BOCHS=y +CONFIG_VGA_PCI=y +CONFIG_OVERRIDE_PCI_ID=y +CONFIG_VGA_VID=0x1b36 +CONFIG_VGA_DID=0x0100 diff --git a/SOURCES/config.vga.ramfb b/SOURCES/config.vga.ramfb new file mode 100644 index 0000000..c809c79 --- /dev/null +++ b/SOURCES/config.vga.ramfb @@ -0,0 +1,3 @@ +CONFIG_BUILD_VGABIOS=y +CONFIG_VGA_RAMFB=y +CONFIG_VGA_PCI=n diff --git a/SOURCES/config.vga.stdvga b/SOURCES/config.vga.stdvga new file mode 100644 index 0000000..7d063b7 --- /dev/null +++ b/SOURCES/config.vga.stdvga @@ -0,0 +1,3 @@ +CONFIG_BUILD_VGABIOS=y +CONFIG_VGA_BOCHS=y +CONFIG_VGA_PCI=y diff --git a/SOURCES/config.vga.virtio b/SOURCES/config.vga.virtio new file mode 100644 index 0000000..aa7a15b --- /dev/null +++ b/SOURCES/config.vga.virtio @@ -0,0 +1,6 @@ +CONFIG_BUILD_VGABIOS=y +CONFIG_VGA_BOCHS=y +CONFIG_VGA_PCI=y +CONFIG_OVERRIDE_PCI_ID=y +CONFIG_VGA_VID=0x1af4 +CONFIG_VGA_DID=0x1050 diff --git a/SOURCES/seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch b/SOURCES/seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch new file mode 100644 index 0000000..11b1f81 --- /dev/null +++ b/SOURCES/seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch @@ -0,0 +1,72 @@ +From 93ba763d219be90b088b15a5fc585ff7f051e424 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann +Date: Mon, 25 Apr 2022 09:25:31 +0200 +Subject: [PATCH 2/2] malloc: use large ZoneHigh when there is enough memory + +RH-Author: Paolo Bonzini +RH-MergeRequest: 9: malloc: use large ZoneHigh when there is enough memory +RH-Bugzilla: 2227373 +RH-Acked-by: Thomas Huth +RH-Acked-by: Oliver Steffen +RH-Acked-by: Laszlo Ersek +RH-Acked-by: Jon Maloy +RH-Commit: [2/2] aa6072543a124ad152199d5263c590cb95609d81 + +In case there is enough memory installed use a large ZoneHigh. + +Signed-off-by: Gerd Hoffmann +(cherry picked from commit dc88f9b72df52b22c35b127b80c487e0b6fca4af) +--- + src/config.h | 3 ++- + src/malloc.c | 14 +++++++++----- + 2 files changed, 11 insertions(+), 6 deletions(-) + +diff --git a/src/config.h b/src/config.h +index 93c8dbc2..9abe355b 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -17,7 +17,8 @@ + // Maximum number of map entries in the e820 map + #define BUILD_MAX_E820 32 + // Space to reserve in high-memory for tables +-#define BUILD_MAX_HIGHTABLE (256*1024) ++#define BUILD_MIN_HIGHTABLE (256*1024) ++#define BUILD_MAX_HIGHTABLE (16*1024*1024) + // Largest supported externaly facing drive id + #define BUILD_MAX_EXTDRIVE 16 + // Number of bytes the smbios may be and still live in the f-segment +diff --git a/src/malloc.c b/src/malloc.c +index ecd8c9ac..da840980 100644 +--- a/src/malloc.c ++++ b/src/malloc.c +@@ -423,7 +423,7 @@ malloc_preinit(void) + + // Populate temp high ram + u32 highram_start = 0; +- u32 highram_size = BUILD_MAX_HIGHTABLE; ++ u32 highram_size = 0; + int i; + for (i=e820_count-1; i>=0; i--) { + struct e820entry *en = &e820_list[i]; +@@ -434,10 +434,14 @@ malloc_preinit(void) + continue; + u32 s = en->start, e = end; + if (!highram_start) { +- u32 newe = ALIGN_DOWN(e - highram_size, MALLOC_MIN_ALIGN); +- if (newe <= e && newe >= s) { +- highram_start = newe; +- e = newe; ++ u32 new_max = ALIGN_DOWN(e - BUILD_MAX_HIGHTABLE, MALLOC_MIN_ALIGN); ++ u32 new_min = ALIGN_DOWN(e - BUILD_MIN_HIGHTABLE, MALLOC_MIN_ALIGN); ++ if (new_max <= e && new_max >= s + BUILD_MAX_HIGHTABLE) { ++ highram_start = e = new_max; ++ highram_size = BUILD_MAX_HIGHTABLE; ++ } else if (new_min <= e && new_min >= s) { ++ highram_start = e = new_min; ++ highram_size = BUILD_MIN_HIGHTABLE; + } + } + alloc_add(&ZoneTmpHigh, s, e); +-- +2.37.3 + diff --git a/SOURCES/seabios-malloc-use-variable-for-ZoneHigh-size.patch b/SOURCES/seabios-malloc-use-variable-for-ZoneHigh-size.patch new file mode 100644 index 0000000..4171bea --- /dev/null +++ b/SOURCES/seabios-malloc-use-variable-for-ZoneHigh-size.patch @@ -0,0 +1,71 @@ +From 2be730cc469be472bc3e3967690a83f1327e9fc1 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann +Date: Mon, 25 Apr 2022 09:20:02 +0200 +Subject: [PATCH 1/2] malloc: use variable for ZoneHigh size + +RH-Author: Paolo Bonzini +RH-MergeRequest: 9: malloc: use large ZoneHigh when there is enough memory +RH-Bugzilla: 2227373 +RH-Acked-by: Thomas Huth +RH-Acked-by: Oliver Steffen +RH-Acked-by: Laszlo Ersek +RH-Acked-by: Jon Maloy +RH-Commit: [1/2] 9e60f2104cc297ed4e78b92c5e5e11e11395bfc3 + +Use the variable highram_size instead of the BUILD_MAX_HIGHTABLE #define +for the ZoneHigh size. Initialize the new variable with the old #define, +so behavior does not change. + +This allows to easily adjust the ZoneHigh size at runtime in a followup +patch. + +Signed-off-by: Gerd Hoffmann +(cherry picked from commit 3b91e8e9fe93d5ff7edf17f984c401f9e6ba55fe) +--- + src/malloc.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/src/malloc.c b/src/malloc.c +index 3733855c..ecd8c9ac 100644 +--- a/src/malloc.c ++++ b/src/malloc.c +@@ -422,7 +422,8 @@ malloc_preinit(void) + e820_add(BUILD_BIOS_ADDR, BUILD_BIOS_SIZE, E820_RESERVED); + + // Populate temp high ram +- u32 highram = 0; ++ u32 highram_start = 0; ++ u32 highram_size = BUILD_MAX_HIGHTABLE; + int i; + for (i=e820_count-1; i>=0; i--) { + struct e820entry *en = &e820_list[i]; +@@ -432,10 +433,10 @@ malloc_preinit(void) + if (en->type != E820_RAM || end > 0xffffffff) + continue; + u32 s = en->start, e = end; +- if (!highram) { +- u32 newe = ALIGN_DOWN(e - BUILD_MAX_HIGHTABLE, MALLOC_MIN_ALIGN); ++ if (!highram_start) { ++ u32 newe = ALIGN_DOWN(e - highram_size, MALLOC_MIN_ALIGN); + if (newe <= e && newe >= s) { +- highram = newe; ++ highram_start = newe; + e = newe; + } + } +@@ -444,9 +445,9 @@ malloc_preinit(void) + + // Populate regions + alloc_add(&ZoneTmpLow, BUILD_STACK_ADDR, BUILD_EBDA_MINIMUM); +- if (highram) { +- alloc_add(&ZoneHigh, highram, highram + BUILD_MAX_HIGHTABLE); +- e820_add(highram, BUILD_MAX_HIGHTABLE, E820_RESERVED); ++ if (highram_start) { ++ alloc_add(&ZoneHigh, highram_start, highram_start + highram_size); ++ e820_add(highram_start, highram_size, E820_RESERVED); + } + } + +-- +2.37.3 + diff --git a/SOURCES/seabios-pci-refactor-the-pci_config_-functions.patch b/SOURCES/seabios-pci-refactor-the-pci_config_-functions.patch new file mode 100644 index 0000000..544298d --- /dev/null +++ b/SOURCES/seabios-pci-refactor-the-pci_config_-functions.patch @@ -0,0 +1,174 @@ +From a35645ca4985b8fdd4f4d8c4d87ae05001061c53 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Volker=20R=C3=BCmelin?= +Date: Sat, 2 Apr 2022 20:28:38 +0200 +Subject: [PATCH 2/3] pci: refactor the pci_config_*() functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 7: pci: fix reset for q35 and tcg +RH-Commit: [1/2] 7607f8f3296435a2884902f650ce060c6be07bd1 +RH-Bugzilla: 2083884 +RH-Acked-by: Pawel Polawski +RH-Acked-by: Oliver Steffen +RH-Acked-by: Igor Mammedov +RH-Acked-by: Laszlo Ersek + +Split out the Standard PCI Configuration Access Mechanism +pci_ioconfig_*() functions from the pci_config_*() functions. +The standard PCI CAM functions will be used in the next patch. + +Reviewed-by: Gerd Hoffmann +Signed-off-by: Volker Rümelin +(cherry picked from commit d24f42b0d819ea473ae05b2f955b822d0126d901) +--- + src/hw/pci.c | 54 ++++++++++++++++++++++++++++++++++++++++------------ + src/hw/pci.h | 12 +++++++++++- + 2 files changed, 53 insertions(+), 13 deletions(-) + +diff --git a/src/hw/pci.c b/src/hw/pci.c +index 3df1dae4..f13cbdea 100644 +--- a/src/hw/pci.c ++++ b/src/hw/pci.c +@@ -26,63 +26,93 @@ static u32 ioconfig_cmd(u16 bdf, u32 addr) + return 0x80000000 | (bdf << 8) | (addr & 0xfc); + } + ++void pci_ioconfig_writel(u16 bdf, u32 addr, u32 val) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ outl(val, PORT_PCI_DATA); ++} ++ + void pci_config_writel(u16 bdf, u32 addr, u32 val) + { + if (!MODESEGMENT && mmconfig) { + writel(mmconfig_addr(bdf, addr), val); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- outl(val, PORT_PCI_DATA); ++ pci_ioconfig_writel(bdf, addr, val); + } + } + ++void pci_ioconfig_writew(u16 bdf, u32 addr, u16 val) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ outw(val, PORT_PCI_DATA + (addr & 2)); ++} ++ + void pci_config_writew(u16 bdf, u32 addr, u16 val) + { + if (!MODESEGMENT && mmconfig) { + writew(mmconfig_addr(bdf, addr), val); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- outw(val, PORT_PCI_DATA + (addr & 2)); ++ pci_ioconfig_writew(bdf, addr, val); + } + } + ++void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ outb(val, PORT_PCI_DATA + (addr & 3)); ++} ++ + void pci_config_writeb(u16 bdf, u32 addr, u8 val) + { + if (!MODESEGMENT && mmconfig) { + writeb(mmconfig_addr(bdf, addr), val); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- outb(val, PORT_PCI_DATA + (addr & 3)); ++ pci_ioconfig_writeb(bdf, addr, val); + } + } + ++u32 pci_ioconfig_readl(u16 bdf, u32 addr) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ return inl(PORT_PCI_DATA); ++} ++ + u32 pci_config_readl(u16 bdf, u32 addr) + { + if (!MODESEGMENT && mmconfig) { + return readl(mmconfig_addr(bdf, addr)); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- return inl(PORT_PCI_DATA); ++ return pci_ioconfig_readl(bdf, addr); + } + } + ++u16 pci_ioconfig_readw(u16 bdf, u32 addr) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ return inw(PORT_PCI_DATA + (addr & 2)); ++} ++ + u16 pci_config_readw(u16 bdf, u32 addr) + { + if (!MODESEGMENT && mmconfig) { + return readw(mmconfig_addr(bdf, addr)); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- return inw(PORT_PCI_DATA + (addr & 2)); ++ return pci_ioconfig_readw(bdf, addr); + } + } + ++u8 pci_ioconfig_readb(u16 bdf, u32 addr) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ return inb(PORT_PCI_DATA + (addr & 3)); ++} ++ + u8 pci_config_readb(u16 bdf, u32 addr) + { + if (!MODESEGMENT && mmconfig) { + return readb(mmconfig_addr(bdf, addr)); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- return inb(PORT_PCI_DATA + (addr & 3)); ++ return pci_ioconfig_readb(bdf, addr); + } + } + +diff --git a/src/hw/pci.h b/src/hw/pci.h +index 01c51f70..ee6acafc 100644 +--- a/src/hw/pci.h ++++ b/src/hw/pci.h +@@ -32,6 +32,15 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 devfn) { + ; BDF >= 0 \ + ; BDF=pci_next(BDF, (BUS))) + ++// standard PCI configration access mechanism ++void pci_ioconfig_writel(u16 bdf, u32 addr, u32 val); ++void pci_ioconfig_writew(u16 bdf, u32 addr, u16 val); ++void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val); ++u32 pci_ioconfig_readl(u16 bdf, u32 addr); ++u16 pci_ioconfig_readw(u16 bdf, u32 addr); ++u8 pci_ioconfig_readb(u16 bdf, u32 addr); ++ ++// PCI configuration access using either PCI CAM or PCIe ECAM + void pci_config_writel(u16 bdf, u32 addr, u32 val); + void pci_config_writew(u16 bdf, u32 addr, u16 val); + void pci_config_writeb(u16 bdf, u32 addr, u8 val); +@@ -39,9 +48,10 @@ u32 pci_config_readl(u16 bdf, u32 addr); + u16 pci_config_readw(u16 bdf, u32 addr); + u8 pci_config_readb(u16 bdf, u32 addr); + void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); +-void pci_enable_mmconfig(u64 addr, const char *name); + u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); + int pci_next(int bdf, int bus); ++ ++void pci_enable_mmconfig(u64 addr, const char *name); + int pci_probe_host(void); + void pci_reboot(void); + +-- +2.35.3 + diff --git a/SOURCES/seabios-reset-force-standard-PCI-configuration-access.patch b/SOURCES/seabios-reset-force-standard-PCI-configuration-access.patch new file mode 100644 index 0000000..d014eb4 --- /dev/null +++ b/SOURCES/seabios-reset-force-standard-PCI-configuration-access.patch @@ -0,0 +1,159 @@ +From a7e5f1d8f1f874434f8b3e6d6eac784d5e3e3971 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Volker=20R=C3=BCmelin?= +Date: Sat, 2 Apr 2022 20:28:39 +0200 +Subject: [PATCH 3/3] reset: force standard PCI configuration access +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 7: pci: fix reset for q35 and tcg +RH-Commit: [2/2] 693fbb9148c81f344dc9f64e7a36e51b42ee1a95 +RH-Bugzilla: 2083884 +RH-Acked-by: Pawel Polawski +RH-Acked-by: Oliver Steffen +RH-Acked-by: Igor Mammedov +RH-Acked-by: Laszlo Ersek + +After a reset of a QEMU -machine q35 guest, the PCI Express +Enhanced Configuration Mechanism is disabled and the variable +mmconfig no longer matches the configuration register PCIEXBAR +of the Q35 chipset. Until the variable mmconfig is reset to 0, +all pci_config_*() functions no longer work. + +The variable mmconfig is located in one of the read-only C-F +segments. To reset it the pci_config_*() functions are needed, +but they do not work. + +Replace all pci_config_*() calls with Standard PCI Configuration +Mechanism pci_ioconfig_*() calls until mmconfig is overwritten +with 0 by a fresh copy of the BIOS. + +This fixes + +In resume (status=0) +In 32bit resume +Attempting a hard reboot +Unable to unlock ram - bridge not found + +and a reset loop with QEMU -accel tcg. + +Signed-off-by: Volker Rümelin +(cherry picked from commit 01774004c7f7fdc9c1e8f1715f70d3b913f8d491) +--- + src/fw/shadow.c | 14 +++++++------- + src/hw/pci.c | 27 +++++++++++++++++++++++++++ + src/hw/pci.h | 6 ++++++ + 3 files changed, 40 insertions(+), 7 deletions(-) + +diff --git a/src/fw/shadow.c b/src/fw/shadow.c +index 4c627a8f..8930616e 100644 +--- a/src/fw/shadow.c ++++ b/src/fw/shadow.c +@@ -32,8 +32,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) + { + // Read in current PAM settings from pci config space + union pamdata_u pamdata; +- pamdata.data32[0] = pci_config_readl(bdf, ALIGN_DOWN(pam0, 4)); +- pamdata.data32[1] = pci_config_readl(bdf, ALIGN_DOWN(pam0, 4) + 4); ++ pamdata.data32[0] = pci_ioconfig_readl(bdf, ALIGN_DOWN(pam0, 4)); ++ pamdata.data32[1] = pci_ioconfig_readl(bdf, ALIGN_DOWN(pam0, 4) + 4); + u8 *pam = &pamdata.data8[pam0 & 0x03]; + + // Make ram from 0xc0000-0xf0000 writable +@@ -46,8 +46,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) + pam[0] = 0x30; + + // Write PAM settings back to pci config space +- pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); +- pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); ++ pci_ioconfig_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); ++ pci_ioconfig_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + + if (!ram_present) + // Copy bios. +@@ -59,7 +59,7 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) + static void + make_bios_writable_intel(u16 bdf, u32 pam0) + { +- int reg = pci_config_readb(bdf, pam0); ++ int reg = pci_ioconfig_readb(bdf, pam0); + if (!(reg & 0x10)) { + // QEMU doesn't fully implement the piix shadow capabilities - + // if ram isn't backing the bios segment when shadowing is +@@ -125,8 +125,8 @@ make_bios_writable(void) + // At this point, statically allocated variables can't be written, + // so do this search manually. + int bdf; +- foreachbdf(bdf, 0) { +- u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID); ++ pci_ioconfig_foreachbdf(bdf, 0) { ++ u32 vendev = pci_ioconfig_readl(bdf, PCI_VENDOR_ID); + u16 vendor = vendev & 0xffff, device = vendev >> 16; + if (vendor == PCI_VENDOR_ID_INTEL + && device == PCI_DEVICE_ID_INTEL_82441) { +diff --git a/src/hw/pci.c b/src/hw/pci.c +index f13cbdea..8eda84b2 100644 +--- a/src/hw/pci.c ++++ b/src/hw/pci.c +@@ -157,6 +157,33 @@ u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) + return 0; + } + ++// Helper function for pci_ioconfig_foreachbdf() macro - return next device ++int pci_ioconfig_next(int bdf, int bus) ++{ ++ if (pci_bdf_to_fn(bdf) == 0 ++ && (pci_ioconfig_readb(bdf, PCI_HEADER_TYPE) & 0x80) == 0) ++ // Last found device wasn't a multi-function device - skip to ++ // the next device. ++ bdf += 8; ++ else ++ bdf += 1; ++ ++ for (;;) { ++ if (pci_bdf_to_bus(bdf) != bus) ++ return -1; ++ ++ u16 v = pci_ioconfig_readw(bdf, PCI_VENDOR_ID); ++ if (v != 0x0000 && v != 0xffff) ++ // Device is present. ++ return bdf; ++ ++ if (pci_bdf_to_fn(bdf) == 0) ++ bdf += 8; ++ else ++ bdf += 1; ++ } ++} ++ + // Helper function for foreachbdf() macro - return next device + int + pci_next(int bdf, int bus) +diff --git a/src/hw/pci.h b/src/hw/pci.h +index ee6acafc..b2f5baf4 100644 +--- a/src/hw/pci.h ++++ b/src/hw/pci.h +@@ -27,6 +27,11 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 devfn) { + return (bus << 8) | devfn; + } + ++#define pci_ioconfig_foreachbdf(BDF, BUS) \ ++ for (BDF=pci_ioconfig_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ ++ ; BDF >= 0 \ ++ ; BDF=pci_ioconfig_next(BDF, (BUS))) ++ + #define foreachbdf(BDF, BUS) \ + for (BDF=pci_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ + ; BDF >= 0 \ +@@ -39,6 +44,7 @@ void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val); + u32 pci_ioconfig_readl(u16 bdf, u32 addr); + u16 pci_ioconfig_readw(u16 bdf, u32 addr); + u8 pci_ioconfig_readb(u16 bdf, u32 addr); ++int pci_ioconfig_next(int bdf, int bus); + + // PCI configuration access using either PCI CAM or PCIe ECAM + void pci_config_writel(u16 bdf, u32 addr, u32 val); +-- +2.35.3 + diff --git a/SOURCES/seabios-shortcut-skip-unbootable-disks-optimitation.patch b/SOURCES/seabios-shortcut-skip-unbootable-disks-optimitation.patch new file mode 100644 index 0000000..4507f66 --- /dev/null +++ b/SOURCES/seabios-shortcut-skip-unbootable-disks-optimitation.patch @@ -0,0 +1,40 @@ +From 27b924ad88b53c1bff736d144b90ce655087d1a5 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann +Date: Fri, 29 Oct 2021 11:19:10 +0200 +Subject: [PATCH 1/3] shortcut skip-unbootable-disks optimitation + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 6: shortcut skip-unbootable-disks optimitation +RH-Commit: [1/1] 95008c119b45b4a360caa4a7733420d72aec99cb +RH-Bugzilla: 2073012 +RH-Acked-by: Laszlo Ersek +RH-Acked-by: Oliver Steffen +RH-Acked-by: Pawel Polawski +--- + src/boot.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/boot.c b/src/boot.c +index 1effd802..b18e7788 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -297,11 +297,16 @@ find_prio(const char *glob) + + u8 is_bootprio_strict(void) + { ++#if 0 + static int prio_halt = -2; + + if (prio_halt == -2) + prio_halt = find_prio("HALT"); + return prio_halt >= 0; ++#else ++ // force initializing all disks ++ return 0; ++#endif + } + + int bootprio_find_pci_device(struct pci_device *pci) +-- +2.35.3 + diff --git a/SOURCES/seabios-virtio-blk-use-larger-default-request-size.patch b/SOURCES/seabios-virtio-blk-use-larger-default-request-size.patch new file mode 100644 index 0000000..d2706c0 --- /dev/null +++ b/SOURCES/seabios-virtio-blk-use-larger-default-request-size.patch @@ -0,0 +1,42 @@ +From 88e527d9fbbbe8d05e45f6db8a151d22e7f973d3 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann +Date: Thu, 30 Jun 2022 17:28:40 +0200 +Subject: [PATCH] virtio-blk: use larger default request size + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 8: virtio-blk: use larger default request size +RH-Commit: [1/1] df68a35a0d02fb91f61eca9e9342ae5f13f99803 +RH-Bugzilla: 2101787 +RH-Acked-by: Oliver Steffen +RH-Acked-by: Pawel Polawski +RH-Acked-by: Miroslav Rezanina + +Bump default from 8 to 64 blocks. Using 8 by default leads +to requests being splitted on qemu, which slows down boot. + +Some (temporary) debug logging added showed that almost all +requests on a standard fedora install are less than 64 blocks, +so that should bring us back to 1.15 performance levels. + +Signed-off-by: Gerd Hoffmann +(cherry picked from commit 46de2eec93bffa0706e6229c0da2919763c8eb04) +--- + src/hw/virtio-blk.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/hw/virtio-blk.c b/src/hw/virtio-blk.c +index 929ba887..9b4a05a4 100644 +--- a/src/hw/virtio-blk.c ++++ b/src/hw/virtio-blk.c +@@ -95,7 +95,7 @@ virtio_blk_op(struct disk_op_s *op, int write) + blk_num_max = (u16)max_io_size / vdrive->drive.blksize; + else + /* default blk_num_max if hardware doesnot advise a proper value */ +- blk_num_max = 8; ++ blk_num_max = 64; + + if (op->count <= blk_num_max) { + virtio_blk_op_one_segment(vdrive, write, sg); +-- +2.31.1 + diff --git a/SPECS/seabios.spec b/SPECS/seabios.spec new file mode 100644 index 0000000..370b387 --- /dev/null +++ b/SPECS/seabios.spec @@ -0,0 +1,441 @@ +Name: seabios +Version: 1.16.0 +Release: 4%{?dist} +Summary: Open-source legacy BIOS implementation + +Group: Applications/Emulators +License: LGPLv3 +URL: https://www.coreboot.org/SeaBIOS + +Source0: https://code.coreboot.org/p/seabios/downloads/get/seabios-1.16.0.tar.gz + +Source10: config.vga.cirrus +Source11: config.vga.qxl +Source12: config.vga.stdvga +Source13: config.vga.virtio +Source14: config.vga.ramfb +Source15: config.vga.bochs-display + +Source20: config.seabios-128k +Source21: config.seabios-256k + +Patch0002: 0002-allow-1TB-of-RAM.patch +Patch0003: 0003-smbios-set-bios-vendor-version-fields-to-Seabios-0.5.patch +Patch0004: 0004-Workaround-for-a-win8.1-32-S4-resume-bug.patch +# For bz#2073012 - Guest whose os is installed multiple disks but boot partition is installed on single disk can't boot into OS on RHEL 8 [rhel-8.7.0] +Patch5: seabios-shortcut-skip-unbootable-disks-optimitation.patch +# For bz#2083884 - qemu reboot problem with seabios 1.16.0 +Patch6: seabios-pci-refactor-the-pci_config_-functions.patch +# For bz#2083884 - qemu reboot problem with seabios 1.16.0 +Patch7: seabios-reset-force-standard-PCI-configuration-access.patch +# For bz#2101787 - [rhel.8.7] Loading a kernel/initrd is sometimes very slow +Patch8: seabios-virtio-blk-use-larger-default-request-size.patch +# For bz#2227373 - "No bootable device" with OS boot disk interface VirtIO-SCSI and with more than 9 VirtIO disks. +Patch9: seabios-malloc-use-variable-for-ZoneHigh-size.patch +# For bz#2227373 - "No bootable device" with OS boot disk interface VirtIO-SCSI and with more than 9 VirtIO disks. +Patch10: seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch + +BuildRequires: python3 iasl +ExclusiveArch: x86_64 %{power64} + +Requires: %{name}-bin = %{version}-%{release} +Requires: seavgabios-bin = %{version}-%{release} + +# Seabios is noarch, but required on architectures which cannot build it. +# Disable debuginfo because it is of no use to us. +%global debug_package %{nil} + +# Similarly, tell RPM to not complain about x86 roms being shipped noarch +%global _binaries_in_noarch_packages_terminate_build 0 + +# You can build a debugging version of the BIOS by setting this to a +# value > 1. See src/config.h for possible values, but setting it to +# a number like 99 will enable all possible debugging. Note that +# debugging goes to a special qemu port that you have to enable. See +# the SeaBIOS top-level README file for the magic qemu invocation to +# enable this. +%global debug_level 1 + + +%description +SeaBIOS is an open-source legacy BIOS implementation which can be used as +a coreboot payload. It implements the standard BIOS calling interfaces +that a typical x86 proprietary BIOS implements. + + +%package bin +Summary: Seabios for x86 +Buildarch: noarch + + +%description bin +SeaBIOS is an open-source legacy BIOS implementation which can be used as +a coreboot payload. It implements the standard BIOS calling interfaces +that a typical x86 proprietary BIOS implements. + + +%package -n seavgabios-bin +Summary: Seavgabios for x86 +Buildarch: noarch +Obsoletes: vgabios < 0.6c-10 + +%description -n seavgabios-bin +SeaVGABIOS is an open-source VGABIOS implementation. + + +%prep +%setup -q +%patch0002 -p1 +%patch0003 -p1 +%patch0004 -p1 +%patch5 -p1 +%patch6 -p1 +%patch7 -p1 +%patch8 -p1 +%patch9 -p1 +%patch10 -p1 + +%build +%ifarch x86_64 +export CFLAGS="$RPM_OPT_FLAGS" +mkdir binaries + +build_bios() { + make PYTHON=%{__python3} clean distclean + cp $1 .config + echo "CONFIG_DEBUG_LEVEL=%{debug_level}" >> .config + make PYTHON=%{__python3} oldnoconfig V=1 EXTRAVERSION="-%release" + + make PYTHON=%{__python3} \ + V=1 \ + $4 \ + EXTRAVERSION="-%{release}" \ + + cp out/$2 binaries/$3 +} + +# seabios +build_bios %{_sourcedir}/config.seabios-128k bios.bin bios.bin +build_bios %{_sourcedir}/config.seabios-256k bios.bin bios-256k.bin + + +# seavgabios +%global vgaconfigs cirrus qxl stdvga virtio ramfb bochs-display +for config in %{vgaconfigs}; do + build_bios %{_sourcedir}/config.vga.${config} \ + vgabios.bin vgabios-${config}.bin out/vgabios.bin +done + + +%install +mkdir -p $RPM_BUILD_ROOT%{_datadir}/seabios +mkdir -p $RPM_BUILD_ROOT%{_datadir}/seavgabios +install -m 0644 binaries/bios.bin $RPM_BUILD_ROOT%{_datadir}/seabios/bios.bin +install -m 0644 binaries/bios-256k.bin $RPM_BUILD_ROOT%{_datadir}/seabios/bios-256k.bin +install -m 0644 binaries/vgabios*.bin $RPM_BUILD_ROOT%{_datadir}/seavgabios + + +%files +%doc COPYING COPYING.LESSER README + + +%files bin +%dir %{_datadir}/seabios/ +%{_datadir}/seabios/bios*.bin + +%files -n seavgabios-bin +%dir %{_datadir}/seavgabios/ +%{_datadir}/seavgabios/vgabios*.bin + +# endif for %ifarch x86_64 {power64} +%endif + + +%changelog +* Thu Aug 03 2023 Jon Maloy - 1.16.0-4 +- seabios-malloc-use-variable-for-ZoneHigh-size.patch [bz#2227373] +- seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch [bz#2227373] +- Resolves: bz#2227373 + ("No bootable device" with OS boot disk interface VirtIO-SCSI and with more than 9 VirtIO disks.) + +* Wed Jul 27 2022 Miroslav Rezanina - 1.16.0-3 +- seabios-virtio-blk-use-larger-default-request-size.patch [bz#2101787] +- Resolves: bz#2101787 + ([rhel.8.7] Loading a kernel/initrd is sometimes very slow) + +* Mon May 30 2022 Jon Maloy - 1.16.0-2 +- seabios-shortcut-skip-unbootable-disks-optimitation.patch [bz#2073012] +- seabios-pci-refactor-the-pci_config_-functions.patch [bz#2083884] +- seabios-reset-force-standard-PCI-configuration-access.patch [bz#2083884] +- Resolves: bz#2073012 + (Guest whose os is installed multiple disks but boot partition is installed on single disk can't boot into OS on RHEL 8 [rhel-8.7.0]) +- Resolves: bz#2083884 + (qemu reboot problem with seabios 1.16.0) + +* Tue Apr 26 2022 Paweł Poławski - 1.16.0-1 +- Rebase to upstream 1.16 tag [bz#2066828] +- Resolves: bz#2066828 + (rebase seabios to 1.16 release) + +* Thu Dec 16 2021 Jon Maloy - 1.15.0-1.el8 +- Rebase to 1.15 (bz#2018392) +- Resolves: bz#2018392 + +* Thu Dec 16 2021 Jon Maloy - 1.15.0-1.el8 +- pci-reserve-resources-for-pcie-pci-bridge-to-fix-reg.patch [bz#2001921] +- pci: let firmware reserve IO for pcie-pci-bridge.patch [bz#2001921] +- Resolves: bz#2001921 + +* Tue Aug 11 2020 Miroslav Rezanina - 1.14.0-1.el8 +- Rebase to 1.14 (bz#1809772) +- Resolves: bz#1809772 + (rebase seabios for RHEL AV-8.3.0) + +* Tue Jan 21 2020 Miroslav Rezanina - 1.13.0-1.el8 +- Rebase to 1.13 (bz#1793377) +- Resolves: bz#1793377 + (rebase seabios to 1.13) + +* Tue Aug 20 2019 Danilo Cesar Lemes de Paula - 1.12.0-5.el8 +- seabios-add-get_keystroke_full-helper.patch [bz#1693031] +- seabios-bootmenu-add-support-for-more-than-9-entries.patch [bz#1693031] +- Resolves: bz#1693031 + (On systems with more than 10 available boot devices, keys are uninintuitive) + +* Fri Aug 02 2019 Danilo Cesar Lemes de Paula - 1.12.0-4.el8 +- seabios-tpm-Check-for-TPM-related-ACPI-tables-before-attempt.patch [bz#1705212] +- seabios-usb-ehci-Clear-pipe-token-on-pipe-reallocate.patch [bz#1705212] +- Resolves: bz#1705212 + (Backport 1.12.1 patches to RHEL-AV 8.1.0) + +* Tue Jul 09 2019 Miroslav Rezanina - 1.12.0-3.el8 +- seabios-rh-add-configs-for-ramfb-and-bochs-display.patch [bz#1724098] +- Resolves: bz#1724098 + (enable device: bochs-display (seabios)) + +* Mon Jan 21 2019 Miroslav Rezanina - 1.12.0-1.el8 +- Rebase to 1.12.0 [bz#1666134] +- Resolves: bz#1666134 + (Rebase seabios for RHEL-AV release in virt:8.0.0 stream) + +* Fri Dec 07 2018 Danilo C. L. de Paula - 1.11.1-3.el8 +- Resolves: bz#1613465 + (Fix seabios package) + +* Fri Aug 24 2018 Danilo C. L. de Paula - 1.11.1-2.el8 +- Resolves: bz#1607349 + (Serial Graphics Adapter show error seabios version) + +* Thu Jul 12 2018 Danilo C. L. de Paula - 1.11.1-1.el8 +- Rebasing seabios 1.11.1 + +* Mon May 21 2018 Danilo C. L. de Paula - 1.11.0-2.el8 +- Syncronizing exploded tree with dist-git + +* Mon Nov 20 2017 Danilo C. L. de Paula - 1.11.0-1.el8 +- Creating RHEL-8.0 initial branch based on 1.11.0 +- Resolves: bz#1515300 +- (Prepare seabios for RHEL-8.0) + +* Fri Nov 17 2017 Paolo Bonzini - 1.11.0-1 +- Rebased to version 1.11.0 +- Add three patches from RHEL + +* Fri Nov 17 2017 Paolo Bonzini - 1.10.2-3 +- Disable cross-compilation on RHEL + +* Thu Jul 27 2017 Fedora Release Engineering - 1.10.2-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Mass_Rebuild + +* Wed Mar 15 2017 Cole Robinson - 1.10.2-1 +- Rebased to version 1.10.2 + +* Sat Feb 11 2017 Fedora Release Engineering - 1.10.1-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_Mass_Rebuild + +* Sun Dec 04 2016 Cole Robinson - 1.10.1-1 +- Rebased to version 1.10.1 + +* Wed Aug 03 2016 Cole Robinson - 1.9.3-1 +- Rebased to version 1.9.3 + +* Thu Mar 24 2016 Paolo Bonzini - 1.9.1-3 +- Include MPT Fusion driver, in preparation for QEMU 2.6 +- Include XHCI and SD in 128k ROM, sacrifice bootsplash instead + +* Thu Mar 17 2016 Cole Robinson - 1.9.1-1 +- Rebased to version 1.9.1 +- Fix incorrect UUID format in boot output (bz #1284259) + +* Thu Feb 04 2016 Fedora Release Engineering - 1.9.0-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_24_Mass_Rebuild + +* Tue Nov 17 2015 Cole Robinson 1.9.0-1 +- Rebased to version 1.9.0 + +* Tue Jul 14 2015 Cole Robinson 1.8.2-1 +- Rebased to version 1.8.2 + +* Fri Jun 19 2015 Fedora Release Engineering - 1.8.1-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_23_Mass_Rebuild + +* Wed Mar 18 2015 Cole Robinson - 1.8.1-1 +- Rebased to version 1.8.1 + +* Sat Feb 21 2015 Cole Robinson - 1.8.0-1 +- Rebased to version 1.8.0 +- Initial support for USB3 hubs +- Initial support for SD cards (on QEMU only) +- Initial support for transitioning to 32bit mode using SMIs (on QEMU TCG + only) +- SeaVGABIOS improvements + +* Sat Nov 15 2014 Cole Robinson - 1.7.5.1-1 +- Update to seabios-1.7.5.1 + +* Wed Jul 09 2014 Cole Robinson - 1.7.5-3 +- Fix PCI-e hotplug (bz #1115598) + +* Sun Jun 08 2014 Fedora Release Engineering - 1.7.5-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_21_Mass_Rebuild + +* Sat May 31 2014 Cole Robinson - 1.7.5-1 +- Rebased to version 1.7.5 +- Support for obtaining SMBIOS tables directly from QEMU. +- XHCI USB controller fixes for real hardware +- seavgabios: New driver for "coreboot native vga" support +- seavgabios: Improved detection of x86emu versions with incorrect + emulation. +- Several bug fixes and code cleanups + +* Wed Mar 26 2014 Matthias Clasen 1.7.4-5 +- Fix booting FreeBSD VMs in virt-manager + +* Mon Mar 17 2014 Cole Robinson 1.7.4-3 +- Build 256k bios images for qemu 2.0 + +* Thu Mar 13 2014 Cole Robinson - 1.7.4-2 +- Fix kvm migration with empty virtio-scsi controller (bz #1032208) + +* Mon Jan 06 2014 Cole Robinson - 1.7.4-1 +- Rebased to version 1.7.4 +- Support for obtaining ACPI tables directly from QEMU. +- Initial support for XHCI USB controllers (initially for QEMU only). +- Support for booting from "pvscsi" devices on QEMU. +- Enhanced floppy driver - improved support for real hardware. +- coreboot cbmem console support. + +* Tue Nov 19 2013 Cole Robinson - 1.7.3.2-1 +- Update to 1.7.3.2 for qemu 1.7 + +* Thu Nov 14 2013 Paolo Bonzini - 1.7.3.1-3 +- Fix pasto in CONFIG_DEBUG_LEVEL. + +* Thu Nov 14 2013 Paolo Bonzini - 1.7.3.1-2 +- Compile as all three of BIOS, CSM and CoreBoot payload. + +* Wed Aug 14 2013 Cole Robinson - 1.7.3.1-1 +- Rebased to version 1.7.3.1 +- Fix USB EHCI detection that was broken in hlist conversion of + PCIDevices. +- Fix bug in CBFS file walking with compressed files. +- acpi: sync FADT flags from PIIX4 to Q35 + +* Sun Aug 04 2013 Fedora Release Engineering - 1.7.3-3 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_20_Mass_Rebuild + +* Tue Jul 09 2013 Cole Robinson - 1.7.3-2 +- Install aml files for use by qemu + +* Mon Jul 08 2013 Cole Robinson - 1.7.3-1 +- Rebased to version 1.7.3 +- Initial support for using SeaBIOS as a UEFI CSM +- Support for detecting and using ACPI reboot ports. +- Non-standard floppy sizes now work again with recent QEMU versions. +- Several bug fixes and code cleanups +- Again fix vgabios obsoletes (bz #981147) + +* Mon May 27 2013 Cole Robinson - 1.7.2.2-1 +- Update to seabios stable 1.7.2.2 +- Obsolete vgabios (bz #967315) + +* Thu Jan 24 2013 Cole Robinson - 1.7.2-1 +- Rebased to version 1.7.2 +- Support for ICH9 host chipset ("q35") on emulators +- Support for booting from LSI MegaRAID SAS controllers +- Support for using the ACPI PM timer on emulators +- Improved Geode VGA BIOS support. +- Several bug fixes + +* Thu Dec 6 2012 Peter Robinson 1.7.1-4 +- Root seabios package is noarch too because it only contains docs + +* Fri Oct 19 2012 Cole Robinson - 1.7.1-3 +- Add seavgabios subpackage + +* Wed Oct 17 2012 Paolo Bonzini - 1.7.1-2 +- Build with cross compiler. Resolves: #866664. + +* Wed Sep 05 2012 Cole Robinson - 1.7.1-1 +- Rebased to version 1.7.1 +- Initial support for booting from USB attached scsi (USB UAS) drives +- USB EHCI 64bit controller support +- USB MSC multi-LUN device support +- Support for booting from LSI SCSI controllers on emulators +- Support for booting from AMD PCscsi controllers on emulators + +* Mon Aug 13 2012 Richard W.M. Jones - 1.7.0-4 +- Modernise and tidy up the RPM. +- Allow debug versions of SeaBIOS to be built easily. + +* Mon Aug 06 2012 Cole Robinson - 1.7.0-3 +- Enable S3/S4 support for guests (it's an F18 feature after all) + +* Sat Jul 21 2012 Fedora Release Engineering - 1.7.0-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_18_Mass_Rebuild + +* Mon May 28 2012 Cole Robinson - 1.7.0-1 +- Rebased to version 1.7.0 +- Support for virtio-scsi +- Improved USB drive support +- Several USB controller bug fixes and improvements + +* Wed Mar 28 2012 Paolo Bonzini - 1.6.3-2 +- Fix bugs in booting from host (or redirected) USB pen drives + +* Wed Feb 08 2012 Justin M. Forbes - 1.6.3-1 +- Update to 1.6.3 upstream +- Add virtio-scsi + +* Sat Jan 14 2012 Fedora Release Engineering - 0.6.2-4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_17_Mass_Rebuild + +* Wed Oct 05 2011 Justin M. Forbes - 0.6.2-3 +- Stop advertising S3 and S4 in DSDT (bz#741375) +- incdule iasl buildreq + +* Wed Jul 13 2011 Justin M. Forbes - 0.6.2-2 +- Fix QXL bug in 0.6.2 + +* Wed Jul 13 2011 Justin M. forbes - 0.6.2-1 +- Update to 0.6.2 upstream for a number of bugfixes + +* Mon Feb 14 2011 Justin M. forbes - 0.6.1-1 +- Update to 0.6.1 upstream for a number of bugfixes + +* Wed Feb 09 2011 Fedora Release Engineering - 0.6.0-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_15_Mass_Rebuild + +* Tue Aug 10 2010 Justin M. Forbes 0.6.0-1 +- Update seabios to latest stable so we can drop patches. + +* Tue Apr 20 2010 Justin M. Forbes 0.5.1-2 +- Ugly hacks to make package noarch and available for arch that cannot build it. +- Disable useless debuginfo + +* Wed Mar 03 2010 Justin M. Forbes 0.5.1-1 +- Update to 0.5.1 stable release +- Pick up patches required for current qemu + +* Thu Jan 07 2010 Justin M. Forbes 0.5.1-0.1.20100108git669c991 +- Created initial package