commit 73d8177ce0d2fcb7693cacee4778d0845ebd3788 Author: sathya priya kumar Date: Thu Jun 13 05:29:09 2024 +0000 rasdaemon: mce-amd-smca: Optimizing decoding of MCA_CTL_SMU bits Optimize smca_smu2_mce_desc in better way from the commit ced615c. Update existing array with extended error descriptions instead of creating new array, simplifying the code. Signed-off-by: Sathya Priya Kumar Signed-off-by: Mauro Carvalho Chehab --- mce-amd-smca.c | 29 +++-------------------------- ras-mce-handler.h | 1 - 2 files changed, 3 insertions(+), 27 deletions(-) --- rasdaemon-0.6.7.orig/mce-amd-smca.c 2024-07-18 11:14:26.008582740 -0400 +++ rasdaemon-0.6.7/mce-amd-smca.c 2024-07-18 11:15:05.510270132 -0400 @@ -397,7 +397,7 @@ static const char * const smca_smu_mce_d "An ECC or parity error in an SMU RAM instance", }; -static const char * smca_smu2_mce_desc[64] = { +static const char * const smca_smu2_mce_desc[] = { "High SRAM ECC or parity error", "Low SRAM ECC or parity error", "Data Cache Bank A ECC or parity error", @@ -410,14 +410,13 @@ static const char * smca_smu2_mce_desc[6 "Instruction Tag Cache Bank B ECC or parity error", "System Hub Read Buffer ECC or parity error", "PHY RAS ECC Error", -}; - -static const char * smca_smu2_ext_mce_desc[] = { + [12 ... 57] = "Reserved", "A correctable error from a GFX Sub-IP", "A fatal error from a GFX Sub-IP", "Reserved", "Reserved", "A poison error from a GFX Sub-IP", + "Reserved", }; static const char * const smca_mp5_mce_desc[] = { @@ -824,27 +823,6 @@ static struct smca_bank_name smca_names[ [SMCA_GMI_PHY] = { "Global Memory Interconnect PHY Unit" }, }; -void smca_smu2_ext_err_desc(void) -{ - int i, j; - int smu2_bits = 62; - - /* - * MCA_CTL_SMU error stings are defined for b'58:59 and b'62 - * in MI300A AMD systems. See AMD PPR MCA::SMU::MCA_CTL_SMU - * - * b'0:11 can be decoded from existing array smca_smu2_mce_desc. - * b'12:57 are Reserved and b'58:62 are appended to the - * smca_smu2_mce_desc. - */ - for (i = 12, j = 0; i < smu2_bits || j < 5; i++, j++) { - for ( ; i < 58; i++) - smca_smu2_mce_desc[i] = "Reserved"; - - smca_smu2_mce_desc[i] = smca_smu2_ext_mce_desc[j]; - } -} - void amd_decode_errcode(struct mce_event *e) { @@ -936,7 +914,6 @@ unsigned short xec = (e->status >> 16) & mcatype_hwid = HWID_MCATYPE(ipid_high & MCI_IPID_HWID, (ipid_high & MCI_IPID_MCATYPE) >> 16); - smca_smu2_ext_err_desc(); fixup_hwid(m, &mcatype_hwid); for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { --- rasdaemon-0.6.7.orig/ras-mce-handler.h 2024-07-18 11:14:26.008582740 -0400 +++ rasdaemon-0.6.7/ras-mce-handler.h 2024-07-18 11:14:28.987559165 -0400 @@ -121,7 +121,6 @@ int set_intel_imc_log(enum cputype cputy /* Undertake AMD SMCA Error Decoding */ void decode_smca_error(struct mce_event *e, struct mce_priv *m); void amd_decode_errcode(struct mce_event *e); -void smca_smu2_ext_err_desc(void); /* Per-CPU-type decoders for Intel CPUs */ void p4_decode_model(struct mce_event *e);