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106 lines
4.1 KiB
106 lines
4.1 KiB
4 months ago
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commit 2d15882a0cbfce0b905039bebc811ac8311cd739
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Author: Muralidhara M K <muralidhara.mk@amd.com>
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Date: Fri Jun 30 11:19:42 2023 +0000
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rasdaemon: Handle reassigned bit definitions for UMC bank
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On some AMD systems some of the existing bit definitions in the
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CTL register of SMCA bank type are reassigned without defining
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new HWID and McaType. Consequently, the errors whose bit
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definitions have been reassigned in the CTL register are being
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erroneously decoded.
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Add new error description structure to compensate for the
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reassigned bit definitions, by new software defined SMCA bank
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type by utilizing the hardware-reserved values for HWID.
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The new SMCA bank type will only be employed for UMC error
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decoding on affected models and the existing error description
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structure for UMC bank type is still valid.
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Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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diff --git a/mce-amd-smca.c b/mce-amd-smca.c
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index fc51b5a..54060ee 100644
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--- a/mce-amd-smca.c
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+++ b/mce-amd-smca.c
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@@ -60,6 +60,7 @@ enum smca_bank_types {
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SMCA_CS_V2_QUIRK,
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SMCA_PIE, /* Power, Interrupts, etc. */
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SMCA_UMC, /* Unified Memory Controller */
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+ SMCA_UMC_QUIRK,
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SMCA_UMC_V2,
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SMCA_MA_LLC, /* Memory Attached Last Level Cache */
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SMCA_PB, /* Parameter Block */
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@@ -313,6 +314,25 @@ static const char * const smca_umc_mce_desc[] = {
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"Read CRC Error",
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};
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+static const char * const smca_umc_quirk_mce_desc[] = {
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+ "DRAM On Die ECC error",
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+ "Data poison error",
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+ "SDP parity error",
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+ "Reserved",
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+ "Address/Command parity error",
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+ "HBM Write data parity error",
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+ "Consolidated SRAM ECC error",
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+ "Reserved",
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+ "Reserved",
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+ "Rdb SRAM ECC error",
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+ "Thermal throttling",
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+ "HBM Read Data Parity error",
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+ "Reserved",
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+ "UMC FW Error",
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+ "SRAM Parity Error",
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+ "HBM CRC Error",
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+};
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+
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static const char * const smca_umc2_mce_desc[] = {
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"DRAM ECC error",
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"Data poison error",
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@@ -642,6 +662,7 @@ static struct smca_mce_desc smca_mce_descs[] = {
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[SMCA_CS_V2_QUIRK] = { smca_cs2_quirk_mce_desc, ARRAY_SIZE(smca_cs2_quirk_mce_desc)},
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[SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
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[SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
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+ [SMCA_UMC_QUIRK] = { smca_umc_quirk_mce_desc, ARRAY_SIZE(smca_umc_quirk_mce_desc) },
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[SMCA_UMC_V2] = { smca_umc2_mce_desc, ARRAY_SIZE(smca_umc2_mce_desc) },
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[SMCA_MA_LLC] = { smca_mall_mce_desc, ARRAY_SIZE(smca_mall_mce_desc) },
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[SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
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@@ -696,6 +717,7 @@ static struct smca_hwid smca_hwid_mcatypes[] = {
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/* Unified Memory Controller MCA type */
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{ SMCA_UMC, 0x00000096 },
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+ { SMCA_UMC_QUIRK, 0x00020000 },
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/* Heterogeneous systems may have both UMC and UMC_v2 types on the same node. */
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{ SMCA_UMC_V2, 0x00010096 },
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/* Memory Attached Last Level Cache */
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@@ -764,7 +786,7 @@ static struct smca_bank_name smca_names[] = {
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[SMCA_L3_CACHE] = { "L3 Cache" },
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[SMCA_CS ... SMCA_CS_V2_QUIRK] = { "Coherent Slave" },
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[SMCA_PIE] = { "Power, Interrupts, etc." },
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- [SMCA_UMC] = { "Unified Memory Controller" },
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+ [SMCA_UMC ... SMCA_UMC_QUIRK] = { "Unified Memory Controller" },
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[SMCA_UMC_V2] = { "Unified Memory Controller V2" },
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[SMCA_MA_LLC] = { "Memory Attached Last Level Cache" },
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[SMCA_PB] = { "Parameter Block" },
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@@ -843,6 +865,10 @@ static inline void fixup_hwid(struct mce_priv* m, uint32_t *hwid_mcatype)
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if (*hwid_mcatype == 0x0002002E)
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*hwid_mcatype = 0x00010000;
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break;
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+ case 0x90 ... 0x9F:
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+ if ((*hwid_mcatype & 0xFF) == 0x00000096)
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+ *hwid_mcatype = 0x00020000;
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+ break;
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default:
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break;
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}
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@@ -908,7 +934,7 @@ void decode_smca_error(struct mce_event *e, struct mce_priv *m)
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smca_mce_descs[bank_type].descs[xec],
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xec);
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- if (bank_type == SMCA_UMC && xec == 0) {
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+ if ((bank_type == SMCA_UMC || bank_type == SMCA_UMC_QUIRK) && xec == 0) {
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channel = find_umc_channel(e);
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csrow = e->synd & 0x7; /* Bit 0, 1 ,2 */
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mce_snprintf(e->mc_location, "memory_channel=%d,csrow=%d",
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