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118 lines
4.0 KiB
118 lines
4.0 KiB
From 6df46774aa41872a706f1a535d5c547a8ef73556 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Thu, 31 Oct 2024 16:52:27 +0800
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Subject: [PATCH 31/38] target/i386: do not rely on ExtSaveArea for
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accelerator-supported XCR0 bits
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 280: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets
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RH-Jira: RHEL-30315 RHEL-45110
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [2/9] 70d54c2101fd1d30a891a414a8c50566c2ddef67 (bonzini/rhel-qemu-kvm)
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Right now, QEMU is using the "feature" and "bits" fields of ExtSaveArea
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to query the accelerator for the support status of extended save areas.
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This is a problem for AVX10, which attaches two feature bits (AVX512F
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and AVX10) to the same extended save states.
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To keep the AVX10 hacks to the minimum, limit usage of esa->features
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and esa->bits. Instead, just query the accelerator for the 0xD leaf.
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Do it in common code and clear esa->size if an extended save state is
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unsupported.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-3-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit b888c7807049cc044d10d70139cb945202fb7cd2)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 33 +++++++++++++++++++++++++++++++--
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target/i386/kvm/kvm-cpu.c | 4 ----
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2 files changed, 31 insertions(+), 6 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index dbdab0f821..d23f15e99a 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -7086,6 +7086,15 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
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#endif
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}
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+static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa)
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+{
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+ if (!esa->size) {
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+ return false;
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+ }
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+
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+ return (env->features[esa->feature] & esa->bits);
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+}
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+
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static void x86_cpu_reset_hold(Object *obj, ResetType type)
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{
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CPUState *cs = CPU(obj);
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@@ -7194,7 +7203,7 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type)
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if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) {
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continue;
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}
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- if (env->features[esa->feature] & esa->bits) {
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+ if (cpuid_has_xsave_feature(env, esa)) {
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xcr0 |= 1ull << i;
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}
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}
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@@ -7332,7 +7341,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
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mask = 0;
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for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
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const ExtSaveArea *esa = &x86_ext_save_areas[i];
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- if (env->features[esa->feature] & esa->bits) {
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+ if (cpuid_has_xsave_feature(env, esa)) {
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mask |= (1ULL << i);
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}
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}
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@@ -8003,6 +8012,26 @@ static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
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static void x86_cpu_post_initfn(Object *obj)
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{
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+ static bool first = true;
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+ uint64_t supported_xcr0;
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+ int i;
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+
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+ if (first) {
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+ first = false;
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+
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+ supported_xcr0 =
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+ ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) |
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+ x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO);
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+
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+ for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {
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+ ExtSaveArea *esa = &x86_ext_save_areas[i];
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+
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+ if (!(supported_xcr0 & (1 << i))) {
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+ esa->size = 0;
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+ }
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+ }
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+ }
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+
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accel_cpu_instance_init(CPU(obj));
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}
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diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
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index 684e731cbc..961b87e98e 100644
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--- a/target/i386/kvm/kvm-cpu.c
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+++ b/target/i386/kvm/kvm-cpu.c
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@@ -143,10 +143,6 @@ static void kvm_cpu_xsave_init(void)
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if (!esa->size) {
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continue;
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}
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- if ((x86_cpu_get_supported_feature_word(NULL, esa->feature) & esa->bits)
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- != esa->bits) {
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- continue;
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- }
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host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx);
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if (eax != 0) {
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assert(esa->size == eax);
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--
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2.39.3
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