You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
51 lines
2.0 KiB
51 lines
2.0 KiB
From 2424960a48dfa6bb499c4cb798b0e5c256deba10 Mon Sep 17 00:00:00 2001
|
|
From: Paolo Bonzini <pbonzini@redhat.com>
|
|
Date: Thu, 31 Oct 2024 16:52:26 +0800
|
|
Subject: [PATCH 30/38] target/i386: cpu: set correct supported XCR0 features
|
|
for TCG
|
|
|
|
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
|
RH-MergeRequest: 280: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets
|
|
RH-Jira: RHEL-30315 RHEL-45110
|
|
RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
|
|
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
RH-Commit: [1/9] 0516319354addebf36f9d364fbae5cda7a98473b (bonzini/rhel-qemu-kvm)
|
|
|
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
|
|
Link: https://lore.kernel.org/r/20241031085233.425388-2-tao1.su@linux.intel.com
|
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
(cherry picked from commit 33098002a838a0450f243f5e17463aca700e923d)
|
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
---
|
|
target/i386/cpu.c | 6 ++++--
|
|
1 file changed, 4 insertions(+), 2 deletions(-)
|
|
|
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
|
index 34e0ce5e62..dbdab0f821 100644
|
|
--- a/target/i386/cpu.c
|
|
+++ b/target/i386/cpu.c
|
|
@@ -1297,7 +1297,9 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
|
.needs_ecx = true, .ecx = 0,
|
|
.reg = R_EAX,
|
|
},
|
|
- .tcg_features = ~0U,
|
|
+ .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK |
|
|
+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
|
|
+ XSTATE_PKRU_MASK,
|
|
.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
|
|
XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
|
|
XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
|
|
@@ -1310,7 +1312,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
|
.needs_ecx = true, .ecx = 0,
|
|
.reg = R_EDX,
|
|
},
|
|
- .tcg_features = ~0U,
|
|
+ .tcg_features = 0U,
|
|
},
|
|
/*Below are MSR exposed features*/
|
|
[FEAT_ARCH_CAPABILITIES] = {
|
|
--
|
|
2.39.3
|
|
|