qemu-kvm/SOURCES/kvm-target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch

From a8180665019d537ee9775614627bf9eb8bd4770e Mon Sep 17 00:00:00 2001
From: Bandan Das <bsd@redhat.com>
Date: Wed, 9 Aug 2023 12:35:33 -0400
Subject: [PATCH 5/7] target/i386: Add missing feature bits in EPYC-Milan model
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RH-Author: Bandan Das <None>
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
RH-Bugzilla: 2094913
RH-Acked-by: Wei Huang <None>
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
RH-Commit: [5/7] 8f77315c8d7010564423df3e3c594c90fd5f9c00 (bdas1/qemu-kvm)

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913

commit 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff
Author: Babu Moger <babu.moger@amd.com>
Date:   Thu May 4 15:53:10 2023 -0500

    target/i386: Add missing feature bits in EPYC-Milan model

    Add the following feature bits for EPYC-Milan model and bump the version.
    vaes            : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
    vpclmulqdq      : Vector VPCLMULQDQ instruction support
    stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
                      performance and may be left Always on
    amd-psfd        : Predictive Store Forward Disable
    no-nested-data-bp         : Processor ignores nested data breakpoints
    lfence-always-serializing : LFENCE instruction is always serializing
    null-sel-clr-base         : Null Selector Clears Base. When this bit is
                                set, a null segment load clears the segment base

    These new features will be added in EPYC-Milan-v2. The "-cpu help" output
    after the change will be.

        x86 EPYC-Milan             (alias configured by machine type)
        x86 EPYC-Milan-v1          AMD EPYC-Milan Processor
        x86 EPYC-Milan-v2          AMD EPYC-Milan Processor

    The documentation for the features are available in the links below.
    a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
       Revision B1 Processors
    b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
    c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
        40332 4.05 Date October 2022

    Signed-off-by: Babu Moger <babu.moger@amd.com>
    Acked-by: Michael S. Tsirkin <mst@redhat.com>
    Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
    Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
    Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
    Message-Id: <20230504205313.225073-6-babu.moger@amd.com>
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Signed-off-by: Bandan Das <bsd@redhat.com>
---
 target/i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7ddebbaa3c..bbddc682df 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1923,6 +1923,56 @@ static const CPUCaches epyc_milan_cache_info = {
     },
 };
 
+static const CPUCaches epyc_milan_v2_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        .type = DATA_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .size = 512 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 1024,
+        .lines_per_tag = 1,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .size = 32 * MiB,
+        .line_size = 64,
+        .associativity = 16,
+        .partitions = 1,
+        .sets = 32768,
+        .lines_per_tag = 1,
+        .self_init = true,
+        .inclusive = true,
+        .complex_indexing = false,
+    },
+};
+
 /* The following VMX features are not supported by KVM and are left out in the
  * CPU definitions:
  *
@@ -4422,6 +4472,26 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC-Milan Processor",
         .cache_info = &epyc_milan_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "model-id",
+                      "AMD EPYC-Milan-v2 Processor" },
+                    { "vaes", "on" },
+                    { "vpclmulqdq", "on" },
+                    { "stibp-always-on", "on" },
+                    { "amd-psfd", "on" },
+                    { "no-nested-data-bp", "on" },
+                    { "lfence-always-serializing", "on" },
+                    { "null-sel-clr-base", "on" },
+                    { /* end of list */ }
+                },
+                .cache_info = &epyc_milan_v2_cache_info
+            },
+            { /* end of list */ }
+        }
     },
 };
 
-- 
2.39.3