qemu-kvm/SOURCES/kvm-target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch

From 95c5cee20741b055dea9ac3ad3176bbaa1eaf705 Mon Sep 17 00:00:00 2001
From: Bandan Das <bsd@redhat.com>
Date: Wed, 9 Aug 2023 12:46:25 -0400
Subject: [PATCH 6/7] target/i386: Add VNMI and automatic IBRS feature bits
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RH-Author: Bandan Das <None>
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
RH-Bugzilla: 2094913
RH-Acked-by: Wei Huang <None>
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
RH-Commit: [6/7] 24c0fb08973aa2615817f67576550ce2efadb75c (bdas1/qemu-kvm)

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913

commit 62a798d4bc2c3e767d94670776c77a7df274d7c5
Author: Babu Moger <babu.moger@amd.com>
Date:   Thu May 4 15:53:11 2023 -0500

    target/i386: Add VNMI and automatic IBRS feature bits

    Add the following featute bits.

    vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the
          guest without using Event Injection mechanism meaning not required to
          track the guest NMI and intercepting the IRET.
          The presence of this feature is indicated via the CPUID function
          0x8000000A_EDX[25].

    automatic-ibrs :
          The AMD Zen4 core supports a new feature called Automatic IBRS.
          It is a "set-and-forget" feature that means that, unlike e.g.,
          s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
          resources automatically across CPL transitions.
          The presence of this feature is indicated via the CPUID function
          0x80000021_EAX[8].

    The documention for the features are available in the links below.
    a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
       Revision B1 Processors
    b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
       40332 4.05 Date October 2022

    Signed-off-by: Santosh Shukla <santosh.shukla@amd.com>
    Signed-off-by: Kim Phillips <kim.phillips@amd.com>
    Signed-off-by: Babu Moger <babu.moger@amd.com>
    Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
    Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
    Message-Id: <20230504205313.225073-7-babu.moger@amd.com>
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Signed-off-by: Bandan Das <bsd@redhat.com>
---
 target/i386/cpu.c | 4 ++--
 target/i386/cpu.h | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index bbddc682df..f1baefe775 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -806,7 +806,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "pfthreshold", "avic", NULL, "v-vmsave-vmload",
             "vgif", NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, "vnmi", NULL, NULL,
             "svme-addr-chk", NULL, NULL, NULL,
         },
         .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
@@ -925,7 +925,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .feat_names = {
             "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
             NULL, NULL, "null-sel-clr-base", NULL,
-            NULL, NULL, NULL, NULL,
+            "auto-ibrs", NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c37abf62ae..f7d225e4f1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -773,6 +773,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 #define CPUID_SVM_AVIC            (1U << 13)
 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
 #define CPUID_SVM_VGIF            (1U << 16)
+#define CPUID_SVM_VNMI            (1U << 25)
 #define CPUID_SVM_SVME_ADDR_CHK   (1U << 28)
 
 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
@@ -948,6 +949,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING    (1U << 2)
 /* Null Selector Clears Base */
 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE    (1U << 6)
+/* Automatic IBRS */
+#define CPUID_8000_0021_EAX_AUTO_IBRS   (1U << 8)
 
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)
-- 
2.39.3