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117 lines
4.0 KiB
117 lines
4.0 KiB
From 31cc494d69449811f4d995326479372da7c1241e Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Mon, 18 Mar 2024 16:53:35 +0100
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Subject: [PATCH 003/100] kvm: add support for guest physical bits
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 245: SEV-SNP support
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RH-Jira: RHEL-39544
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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RH-Acked-by: Bandan Das <bdas@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Commit: [3/91] abb1ba3a584152d8efabd8255b86afe609f8ffbd (bonzini/rhel-qemu-kvm)
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Query kvm for supported guest physical address bits, in cpuid
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function 80000008, eax[23:16]. Usually this is identical to host
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physical address bits. With NPT or EPT being used this might be
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restricted to 48 (max 4-level paging address space size) even if
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the host cpu supports more physical address bits.
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When set pass this to the guest, using cpuid too. Guest firmware
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can use this to figure how big the usable guest physical address
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space is, so PCI bar mapping are actually reachable.
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Message-ID: <20240318155336.156197-2-kraxel@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 0d08c423688edcca857f88dab20f1fc56de2b281)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/kvm/kvm-cpu.c | 50 ++++++++++++++++++++++++++++++++-------
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1 file changed, 42 insertions(+), 8 deletions(-)
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diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
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index b91af5051f..7ef94c681f 100644
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--- a/target/i386/kvm/kvm-cpu.c
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+++ b/target/i386/kvm/kvm-cpu.c
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@@ -18,10 +18,32 @@
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#include "kvm_i386.h"
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#include "hw/core/accel-cpu.h"
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+static void kvm_set_guest_phys_bits(CPUState *cs)
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+{
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+ X86CPU *cpu = X86_CPU(cs);
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+ uint32_t eax, guest_phys_bits;
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+
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+ eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x80000008, 0, R_EAX);
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+ guest_phys_bits = (eax >> 16) & 0xff;
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+ if (!guest_phys_bits) {
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+ return;
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+ }
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+ cpu->guest_phys_bits = guest_phys_bits;
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+ if (cpu->guest_phys_bits > cpu->phys_bits) {
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+ cpu->guest_phys_bits = cpu->phys_bits;
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+ }
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+
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+ if (cpu->host_phys_bits && cpu->host_phys_bits_limit &&
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+ cpu->guest_phys_bits > cpu->host_phys_bits_limit) {
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+ cpu->guest_phys_bits = cpu->host_phys_bits_limit;
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+ }
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+}
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+
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static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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+ bool ret;
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/*
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* The realize order is important, since x86_cpu_realize() checks if
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@@ -32,13 +54,15 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
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*
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* realize order:
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*
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- * x86_cpu_realize():
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- * -> x86_cpu_expand_features()
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- * -> cpu_exec_realizefn():
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- * -> accel_cpu_common_realize()
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- * kvm_cpu_realizefn() -> host_cpu_realizefn()
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- * -> cpu_common_realizefn()
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- * -> check/update ucode_rev, phys_bits, mwait
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+ * x86_cpu_realizefn():
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+ * x86_cpu_expand_features()
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+ * cpu_exec_realizefn():
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+ * accel_cpu_common_realize()
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+ * kvm_cpu_realizefn()
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+ * host_cpu_realizefn()
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+ * kvm_set_guest_phys_bits()
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+ * check/update ucode_rev, phys_bits, guest_phys_bits, mwait
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+ * cpu_common_realizefn() (via xcc->parent_realize)
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*/
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if (cpu->max_features) {
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if (enable_cpu_pm && kvm_has_waitpkg()) {
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@@ -50,7 +74,17 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
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MSR_IA32_UCODE_REV);
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}
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}
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- return host_cpu_realizefn(cs, errp);
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+ ret = host_cpu_realizefn(cs, errp);
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+ if (!ret) {
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+ return ret;
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+ }
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+
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+ if ((env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) &&
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+ cpu->guest_phys_bits == -1) {
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+ kvm_set_guest_phys_bits(cs);
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+ }
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+
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+ return true;
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}
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static bool lmce_supported(void)
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--
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2.39.3
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