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72 lines
2.7 KiB
72 lines
2.7 KiB
From 9cfedd3a9880390ddda25a235b999430c3dd5e83 Mon Sep 17 00:00:00 2001
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From: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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Date: Wed, 24 May 2023 07:25:57 -0400
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Subject: [PATCH 13/15] target/i386: add support for FLUSH_L1D feature
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RH-Author: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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RH-MergeRequest: 281: target/i386: add support for FLUSH_L1D feature
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RH-Bugzilla: 2216203
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Acked-by: Jon Maloy <jmaloy@redhat.com>
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RH-Commit: [1/2] 50c54ca7c734dc2b9303e724a6c5ac1127472271
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2216203
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commit 0e7e3bf1a552c178924867fa7c2f30ccc8a179e0
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Author: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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Date: Wed Feb 1 08:57:58 2023 -0500
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target/i386: add support for FLUSH_L1D feature
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As reported by Intel's doc:
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"L1D_FLUSH: Writeback and invalidate the L1 data cache"
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If this cpu feature is present in host, allow QEMU to choose whether to
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show it to the guest too.
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One disadvantage of not exposing it is that the guest will report
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a non existing vulnerability in
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/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
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because the mitigation is present only when the cpu has
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(FLUSH_L1D and MD_CLEAR) or FB_CLEAR
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features enabled.
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Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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Message-Id: <20230201135759.555607-2-eesposit@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 0543b846ff..47da059df6 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -857,7 +857,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
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NULL, NULL, "amx-bf16", "avx512-fp16",
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"amx-tile", "amx-int8", "spec-ctrl", "stibp",
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- NULL, "arch-capabilities", "core-capability", "ssbd",
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+ "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
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},
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.cpuid = {
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.eax = 7,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 5d2ddd81b9..7cb7cea8ab 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -864,6 +864,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Single Thread Indirect Branch Predictors */
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#define CPUID_7_0_EDX_STIBP (1U << 27)
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+/* Flush L1D cache */
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+#define CPUID_7_0_EDX_FLUSH_L1D (1U << 28)
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/* Arch Capabilities */
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#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
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/* Core Capability */
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--
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2.37.3
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