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179 lines
5.7 KiB
179 lines
5.7 KiB
From 90a276ed72deab84f3fdd4b57e9ccfc6514934fb Mon Sep 17 00:00:00 2001
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From: Zeng Guang <guang.zeng@intel.com>
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Date: Wed, 16 Feb 2022 22:04:33 -0800
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Subject: [PATCH 11/24] x86: Support XFD and AMX xsave data migration
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RH-Author: Paul Lai <plai@redhat.com>
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RH-MergeRequest: 176: Enable KVM AMX support
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RH-Commit: [11/13] 4ff6e5544ffdac4e6d2f568f7f63b937502ca6c5
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RH-Bugzilla: 1916415
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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XFD(eXtended Feature Disable) allows to enable a
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feature on xsave state while preventing specific
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user threads from using the feature.
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Support save and restore XFD MSRs if CPUID.D.1.EAX[4]
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enumerate to be valid. Likewise migrate the MSRs and
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related xsave state necessarily.
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Signed-off-by: Zeng Guang <guang.zeng@intel.com>
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Signed-off-by: Wei Wang <wei.w.wang@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-8-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit cdec2b753b487d9e8aab028231c35d87789ea083)
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Signed-off-by: Paul Lai <plai@redhat.com>
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---
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target/i386/cpu.h | 9 +++++++++
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target/i386/kvm/kvm.c | 18 +++++++++++++++++
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target/i386/machine.c | 46 +++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 73 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 14a3501b87..8ab2a4042a 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -505,6 +505,9 @@ typedef enum X86Seg {
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#define MSR_VM_HSAVE_PA 0xc0010117
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+#define MSR_IA32_XFD 0x000001c4
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+#define MSR_IA32_XFD_ERR 0x000001c5
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+
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#define MSR_IA32_BNDCFGS 0x00000d90
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#define MSR_IA32_XSS 0x00000da0
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#define MSR_IA32_UMWAIT_CONTROL 0xe1
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@@ -870,6 +873,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
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/* AVX512 BFloat16 Instruction */
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
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+/* XFD Extend Feature Disabled */
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+#define CPUID_D_1_EAX_XFD (1U << 4)
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/* Packets which contain IP payload have LIP values */
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#define CPUID_14_0_ECX_LIP (1U << 31)
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@@ -1610,6 +1615,10 @@ typedef struct CPUX86State {
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uint64_t msr_rtit_cr3_match;
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uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
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+ /* Per-VCPU XFD MSRs */
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+ uint64_t msr_xfd;
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+ uint64_t msr_xfd_err;
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+
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/* exception/interrupt handling */
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int error_code;
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int exception_is_int;
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diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
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index d3d476df27..b1128b0e07 100644
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--- a/target/i386/kvm/kvm.c
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+++ b/target/i386/kvm/kvm.c
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@@ -3219,6 +3219,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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env->msr_ia32_sgxlepubkeyhash[3]);
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}
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+ if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_XFD,
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+ env->msr_xfd);
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+ kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
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+ env->msr_xfd_err);
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+ }
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+
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/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
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* kvm_put_msr_feature_control. */
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}
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@@ -3571,6 +3578,11 @@ static int kvm_get_msrs(X86CPU *cpu)
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kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
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}
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+ if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
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+ kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
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+ }
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+
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ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
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if (ret < 0) {
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return ret;
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@@ -3870,6 +3882,12 @@ static int kvm_get_msrs(X86CPU *cpu)
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env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
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msrs[i].data;
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break;
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+ case MSR_IA32_XFD:
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+ env->msr_xfd = msrs[i].data;
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+ break;
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+ case MSR_IA32_XFD_ERR:
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+ env->msr_xfd_err = msrs[i].data;
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+ break;
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}
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}
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diff --git a/target/i386/machine.c b/target/i386/machine.c
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index 83c2b91529..3977e9d8f8 100644
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--- a/target/i386/machine.c
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+++ b/target/i386/machine.c
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@@ -1455,6 +1455,48 @@ static const VMStateDescription vmstate_msr_intel_sgx = {
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}
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};
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+static bool xfd_msrs_needed(void *opaque)
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+{
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+ X86CPU *cpu = opaque;
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+ CPUX86State *env = &cpu->env;
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+
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+ return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD);
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+}
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+
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+static const VMStateDescription vmstate_msr_xfd = {
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+ .name = "cpu/msr_xfd",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = xfd_msrs_needed,
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+ .fields = (VMStateField[]) {
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+ VMSTATE_UINT64(env.msr_xfd, X86CPU),
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+ VMSTATE_UINT64(env.msr_xfd_err, X86CPU),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+
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+#ifdef TARGET_X86_64
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+static bool amx_xtile_needed(void *opaque)
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+{
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+ X86CPU *cpu = opaque;
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+ CPUX86State *env = &cpu->env;
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+
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+ return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE);
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+}
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+
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+static const VMStateDescription vmstate_amx_xtile = {
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+ .name = "cpu/intel_amx_xtile",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = amx_xtile_needed,
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+ .fields = (VMStateField[]) {
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+ VMSTATE_UINT8_ARRAY(env.xtilecfg, X86CPU, 64),
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+ VMSTATE_UINT8_ARRAY(env.xtiledata, X86CPU, 8192),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+#endif
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+
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const VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.version_id = 12,
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@@ -1593,6 +1635,10 @@ const VMStateDescription vmstate_x86_cpu = {
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#endif
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&vmstate_msr_tsx_ctrl,
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&vmstate_msr_intel_sgx,
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+ &vmstate_msr_xfd,
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+#ifdef TARGET_X86_64
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+ &vmstate_amx_xtile,
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+#endif
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NULL
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}
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};
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--
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2.35.3
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