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79 lines
3.1 KiB
79 lines
3.1 KiB
From 19504ea76b6341c11213316402bb5194487e1f01 Mon Sep 17 00:00:00 2001
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From: Bandan Das <bsd@redhat.com>
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Date: Thu, 3 Aug 2023 15:13:19 -0400
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Subject: [PATCH 3/5] i386/sev: Update checks and information related to
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reduced-phys-bits
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RH-Author: Bandan Das <None>
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RH-MergeRequest: 296: Updates to SEV reduced-phys-bits parameter
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RH-Bugzilla: 2214840
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RH-Acked-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Commit: [3/4] b617173d2b15fa39cdc02b5c1ac4d52e9b0dfede
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2214840
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commit 8168fed9f84e3128f7628969ae78af49433d5ce7
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Author: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Fri Sep 30 10:14:29 2022 -0500
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i386/sev: Update checks and information related to reduced-phys-bits
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The value of the reduced-phys-bits parameter is propogated to the CPUID
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information exposed to the guest. Update the current validation check to
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account for the size of the CPUID field (6-bits), ensuring the value is
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in the range of 1 to 63.
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Maintain backward compatibility, to an extent, by allowing a value greater
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than 1 (so that the previously documented value of 5 still works), but not
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allowing anything over 63.
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Fixes: d8575c6c02 ("sev/i386: add command to initialize the memory encryption context")
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Message-Id: <cca5341a95ac73f904e6300f10b04f9c62e4e8ff.1664550870.git.thomas.lendacky@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Bandan Das <bsd@redhat.com>
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---
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target/i386/sev.c | 17 ++++++++++++++---
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1 file changed, 14 insertions(+), 3 deletions(-)
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diff --git a/target/i386/sev.c b/target/i386/sev.c
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index 025ff7a6f8..ba6a65e90c 100644
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--- a/target/i386/sev.c
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+++ b/target/i386/sev.c
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@@ -892,15 +892,26 @@ int sev_kvm_init(ConfidentialGuestSupport *cgs, Error **errp)
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host_cpuid(0x8000001F, 0, NULL, &ebx, NULL, NULL);
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host_cbitpos = ebx & 0x3f;
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+ /*
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+ * The cbitpos value will be placed in bit positions 5:0 of the EBX
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+ * register of CPUID 0x8000001F. No need to verify the range as the
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+ * comparison against the host value accomplishes that.
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+ */
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if (host_cbitpos != sev->cbitpos) {
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error_setg(errp, "%s: cbitpos check failed, host '%d' requested '%d'",
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__func__, host_cbitpos, sev->cbitpos);
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goto err;
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}
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- if (sev->reduced_phys_bits < 1) {
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- error_setg(errp, "%s: reduced_phys_bits check failed, it should be >=1,"
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- " requested '%d'", __func__, sev->reduced_phys_bits);
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+ /*
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+ * The reduced-phys-bits value will be placed in bit positions 11:6 of
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+ * the EBX register of CPUID 0x8000001F, so verify the supplied value
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+ * is in the range of 1 to 63.
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+ */
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+ if (sev->reduced_phys_bits < 1 || sev->reduced_phys_bits > 63) {
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+ error_setg(errp, "%s: reduced_phys_bits check failed,"
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+ " it should be in the range of 1 to 63, requested '%d'",
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+ __func__, sev->reduced_phys_bits);
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goto err;
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}
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--
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2.37.3
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