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206 lines
7.3 KiB
206 lines
7.3 KiB
From 54d3e58aabf9716f9a07aeb7044d7b7997e28123 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Tue, 31 Jan 2023 09:48:03 +0100
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Subject: [PATCH 5/8] target/i386: fix ADOX followed by ADCX
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions
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RH-Bugzilla: 2173590
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RH-Acked-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Bandan Das <None>
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RH-Commit: [5/7] 64dbe4e602f08e4a88fdeacee5a8993ca4383563 (bonzini/rhel-qemu-kvm)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590
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Upstream-Status: merged
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When ADCX is followed by ADOX or vice versa, the second instruction's
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carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX
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operation. Retrieving the carry from EFLAGS is handled by this bit
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of gen_ADCOX:
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tcg_gen_extract_tl(carry_in, cpu_cc_src,
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ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1);
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Unfortunately, in this case cc_op has been overwritten by the previous
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"if" statement to CC_OP_ADCOX. This works by chance when the first
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instruction is ADCX; however, if the first instruction is ADOX,
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ADCX will incorrectly take its carry from OF instead of CF.
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Fix by moving the computation of the new cc_op at the end of the function.
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The included exhaustive test case fails without this patch and passes
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afterwards.
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Because ADCX/ADOX need not be invoked through the VEX prefix, this
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regression bisects to commit 16fc5726a6e2 ("target/i386: reimplement
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0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a
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little earlier, when BMI instructions were rewritten using the new
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decoder framework.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471
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Reported-by: Paul Jolly <https://gitlab.com/myitcv>
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Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18)
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 60c7dd22e1383754d5f150bc9f7c2785c662a7b6)
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---
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target/i386/tcg/emit.c.inc | 20 +++++----
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tests/tcg/i386/Makefile.target | 6 ++-
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tests/tcg/i386/test-i386-adcox.c | 75 ++++++++++++++++++++++++++++++++
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3 files changed, 91 insertions(+), 10 deletions(-)
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create mode 100644 tests/tcg/i386/test-i386-adcox.c
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diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
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index 4d7702c106..0d7c6e80ae 100644
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--- a/target/i386/tcg/emit.c.inc
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+++ b/target/i386/tcg/emit.c.inc
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@@ -1015,6 +1015,7 @@ VSIB_AVX(VPGATHERQ, vpgatherq)
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static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
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{
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+ int opposite_cc_op;
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TCGv carry_in = NULL;
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TCGv carry_out = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2);
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TCGv zero;
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@@ -1022,14 +1023,8 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
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if (cc_op == s->cc_op || s->cc_op == CC_OP_ADCOX) {
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/* Re-use the carry-out from a previous round. */
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carry_in = carry_out;
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- cc_op = s->cc_op;
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- } else if (s->cc_op == CC_OP_ADCX || s->cc_op == CC_OP_ADOX) {
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- /* Merge with the carry-out from the opposite instruction. */
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- cc_op = CC_OP_ADCOX;
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- }
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-
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- /* If we don't have a carry-in, get it out of EFLAGS. */
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- if (!carry_in) {
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+ } else {
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+ /* We don't have a carry-in, get it out of EFLAGS. */
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if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) {
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gen_compute_eflags(s);
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}
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@@ -1053,7 +1048,14 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
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tcg_gen_add2_tl(s->T0, carry_out, s->T0, carry_out, s->T1, zero);
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break;
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}
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- set_cc_op(s, cc_op);
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+
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+ opposite_cc_op = cc_op == CC_OP_ADCX ? CC_OP_ADOX : CC_OP_ADCX;
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+ if (s->cc_op == CC_OP_ADCOX || s->cc_op == opposite_cc_op) {
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+ /* Merge with the carry-out from the opposite instruction. */
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+ set_cc_op(s, CC_OP_ADCOX);
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+ } else {
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+ set_cc_op(s, cc_op);
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+ }
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}
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static void gen_ADCX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target
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index 81831cafbc..bafd8c2180 100644
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--- a/tests/tcg/i386/Makefile.target
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+++ b/tests/tcg/i386/Makefile.target
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@@ -14,7 +14,7 @@ config-cc.mak: Makefile
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I386_SRCS=$(notdir $(wildcard $(I386_SRC)/*.c))
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ALL_X86_TESTS=$(I386_SRCS:.c=)
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SKIP_I386_TESTS=test-i386-ssse3 test-avx test-3dnow test-mmx
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-X86_64_TESTS:=$(filter test-i386-bmi2 $(SKIP_I386_TESTS), $(ALL_X86_TESTS))
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+X86_64_TESTS:=$(filter test-i386-adcox test-i386-bmi2 $(SKIP_I386_TESTS), $(ALL_X86_TESTS))
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test-i386-sse-exceptions: CFLAGS += -msse4.1 -mfpmath=sse
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run-test-i386-sse-exceptions: QEMU_OPTS += -cpu max
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@@ -28,6 +28,10 @@ test-i386-bmi2: CFLAGS=-O2
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run-test-i386-bmi2: QEMU_OPTS += -cpu max
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run-plugin-test-i386-bmi2-%: QEMU_OPTS += -cpu max
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+test-i386-adcox: CFLAGS=-O2
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+run-test-i386-adcox: QEMU_OPTS += -cpu max
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+run-plugin-test-i386-adcox-%: QEMU_OPTS += -cpu max
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+
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#
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# hello-i386 is a barebones app
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#
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diff --git a/tests/tcg/i386/test-i386-adcox.c b/tests/tcg/i386/test-i386-adcox.c
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new file mode 100644
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index 0000000000..16169efff8
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--- /dev/null
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+++ b/tests/tcg/i386/test-i386-adcox.c
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@@ -0,0 +1,75 @@
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+/* See if various BMI2 instructions give expected results */
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+#include <assert.h>
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+#include <stdint.h>
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+#include <stdio.h>
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+
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+#define CC_C 1
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+#define CC_O (1 << 11)
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+
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+#ifdef __x86_64__
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+#define REG uint64_t
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+#else
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+#define REG uint32_t
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+#endif
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+
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+void test_adox_adcx(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand)
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+{
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+ REG flags;
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+ REG out_adcx, out_adox;
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+
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+ asm("pushf; pop %0" : "=r"(flags));
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+ flags &= ~(CC_C | CC_O);
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+ flags |= (in_c ? CC_C : 0);
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+ flags |= (in_o ? CC_O : 0);
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+
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+ out_adcx = adcx_operand;
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+ out_adox = adox_operand;
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+ asm("push %0; popf;"
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+ "adox %3, %2;"
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+ "adcx %3, %1;"
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+ "pushf; pop %0"
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+ : "+r" (flags), "+r" (out_adcx), "+r" (out_adox)
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+ : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
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+
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+ assert(out_adcx == in_c + adcx_operand - 1);
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+ assert(out_adox == in_o + adox_operand - 1);
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+ assert(!!(flags & CC_C) == (in_c || adcx_operand));
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+ assert(!!(flags & CC_O) == (in_o || adox_operand));
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+}
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+
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+void test_adcx_adox(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand)
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+{
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+ REG flags;
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+ REG out_adcx, out_adox;
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+
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+ asm("pushf; pop %0" : "=r"(flags));
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+ flags &= ~(CC_C | CC_O);
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+ flags |= (in_c ? CC_C : 0);
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+ flags |= (in_o ? CC_O : 0);
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+
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+ out_adcx = adcx_operand;
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+ out_adox = adox_operand;
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+ asm("push %0; popf;"
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+ "adcx %3, %1;"
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+ "adox %3, %2;"
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+ "pushf; pop %0"
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+ : "+r" (flags), "+r" (out_adcx), "+r" (out_adox)
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+ : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
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+
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+ assert(out_adcx == in_c + adcx_operand - 1);
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+ assert(out_adox == in_o + adox_operand - 1);
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+ assert(!!(flags & CC_C) == (in_c || adcx_operand));
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+ assert(!!(flags & CC_O) == (in_o || adox_operand));
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+}
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+
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+int main(int argc, char *argv[]) {
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+ /* try all combinations of input CF, input OF, CF from op1+op2, OF from op2+op1 */
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+ int i;
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+ for (i = 0; i <= 15; i++) {
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+ printf("%d\n", i);
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+ test_adcx_adox(!!(i & 1), !!(i & 2), !!(i & 4), !!(i & 8));
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+ test_adox_adcx(!!(i & 1), !!(i & 2), !!(i & 4), !!(i & 8));
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+ }
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+ return 0;
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+}
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+
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--
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2.39.1
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