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95 lines
3.9 KiB
95 lines
3.9 KiB
1 year ago
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From 2d7fb99c02a7666f1d8fe70a4749f0b7771a68ed Mon Sep 17 00:00:00 2001
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From: Bandan Das <bsd@redhat.com>
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Date: Wed, 9 Aug 2023 12:29:55 -0400
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Subject: [PATCH 3/7] target/i386: Add a couple of feature bits in
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8000_0008_EBX
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RH-Author: Bandan Das <None>
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RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
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RH-Bugzilla: 2094913
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RH-Acked-by: Wei Huang <None>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [3/7] b11020b249d4ecc2e3e1ddf4fdc4b52c42ec2642 (bdas1/qemu-kvm)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
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commit bb039a230e6a7920d71d21fa9afee2653a678c48
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Author: Babu Moger <babu.moger@amd.com>
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Date: Thu May 4 15:53:08 2023 -0500
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target/i386: Add a couple of feature bits in 8000_0008_EBX
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Add the following feature bits.
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amd-psfd : Predictive Store Forwarding Disable:
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PSF is a hardware-based micro-architectural optimization
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designed to improve the performance of code execution by
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predicting address dependencies between loads and stores.
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While SSBD (Speculative Store Bypass Disable) disables both
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PSF and speculative store bypass, PSFD only disables PSF.
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PSFD may be desirable for the software which is concerned
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with the speculative behavior of PSF but desires a smaller
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performance impact than setting SSBD.
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Depends on the following kernel commit:
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b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable")
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stibp-always-on :
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Single Thread Indirect Branch Prediction mode has enhanced
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performance and may be left always on.
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The documentation for the features are available in the links below.
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a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
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Revision B1 Processors
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b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Acked-by: Michael S. Tsirkin <mst@redhat.com>
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Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
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Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
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Message-Id: <20230504205313.225073-4-babu.moger@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Bandan Das <bsd@redhat.com>
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---
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target/i386/cpu.c | 4 ++--
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target/i386/cpu.h | 4 ++++
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2 files changed, 6 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 8aa7eb611c..c8f88aefc7 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -911,10 +911,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, "wbnoinvd", NULL, NULL,
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"ibpb", NULL, "ibrs", "amd-stibp",
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- NULL, NULL, NULL, NULL,
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+ NULL, "stibp-always-on", NULL, NULL,
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NULL, NULL, NULL, NULL,
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"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
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- NULL, NULL, NULL, NULL,
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+ "amd-psfd", NULL, NULL, NULL,
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},
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.cpuid = { .eax = 0x80000008, .reg = R_EBX, },
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.tcg_features = 0,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index c28b9df217..81d2200543 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -934,8 +934,12 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_8000_0008_EBX_IBRS (1U << 14)
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/* Single Thread Indirect Branch Predictors */
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#define CPUID_8000_0008_EBX_STIBP (1U << 15)
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+/* STIBP mode has enhanced performance and may be left always on */
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+#define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
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/* Speculative Store Bypass Disable */
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#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
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+/* Predictive Store Forwarding Disable */
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+#define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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--
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2.39.3
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