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60 lines
2.0 KiB
60 lines
2.0 KiB
2 years ago
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From ccaa1135bd1aa90c94f0e8b5417bd2a420134e6c Mon Sep 17 00:00:00 2001
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From: Jon Maloy <jmaloy@redhat.com>
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Date: Wed, 30 Mar 2022 14:52:34 -0400
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Subject: [PATCH 08/18] i386: Add Icelake-Server-v6 CPU model with 5-level EPT
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support
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RH-Author: Jon Maloy <jmaloy@redhat.com>
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RH-MergeRequest: 139: vmxcap: Add 5-level EPT bit
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RH-Commit: [2/2] e913746b2df9cbd0308014ab5cc72577458857fa (jmaloy/qemu-kvm)
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RH-Bugzilla: 2065207
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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BZ: https://bugzilla.redhat.com/show_bug.cgi?id=2065207
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UPSTREAM: Merged
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commit: 12cab535db6440af41ed8dfefe908a594321b6ce
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Author: Vitaly Kuznetsov <vkuznets@redhat.com>
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Date: Mon Feb 21 15:53:15 2022 +0100
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i386: Add Icelake-Server-v6 CPU model with 5-level EPT support
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Windows 11 with WSL2 enabled (Hyper-V) fails to boot with Icelake-Server
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{-v5} CPU model but boots well with '-cpu host'. Apparently, it expects
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5-level paging and 5-level EPT support to come in pair but QEMU's
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Icelake-Server CPU model lacks the later. Introduce 'Icelake-Server-v6'
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CPU model with 'vmx-page-walk-5' enabled by default.
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Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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Message-Id: <20220221145316.576138-1-vkuznets@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 12cab535db6440af41ed8dfefe908a594321b6ce)
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Signed-off-by: Jon Maloy <jmaloy@redhat.com>
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---
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target/i386/cpu.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index aa9e636800..6e25d13339 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -3505,6 +3505,14 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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},
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},
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+ {
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+ .version = 6,
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+ .note = "5-level EPT",
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+ .props = (PropValue[]) {
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+ { "vmx-page-walk-5", "on" },
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+ { /* end of list */ }
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+ },
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+ },
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{ /* end of list */ }
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}
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},
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--
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2.27.0
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