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78 lines
3.7 KiB
78 lines
3.7 KiB
2 years ago
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From f4ddcdd2395e0944c20f6683c66068ed0ac7d757 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Sat, 7 Jan 2023 18:14:20 +0100
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Subject: [PATCH 1/8] target/i386: fix operand size of unary SSE operations
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions
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RH-Bugzilla: 2173590
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RH-Acked-by: Emanuele Giuseppe Esposito <eesposit@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Bandan Das <None>
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RH-Commit: [1/7] 7041f3e30e19add6bd8e5355d8bebf92390a5c2e (bonzini/rhel-qemu-kvm)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590
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Upstream-Status: merged
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VRCPSS, VRSQRTSS and VCVTSx2Sx have a 32-bit or 64-bit memory operand,
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which is represented in the decoding tables by X86_VEX_REPScalar. Add it
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to the tables, and make validate_vex() handle the case of an instruction
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that is in exception type 4 without the REP prefix and exception type 5
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with it; this is the cas of VRCP and VRSQRT.
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Reported-by: yongwoo <https://gitlab.com/yongwoo36>
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1377
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 3d304620ec6c95f31db17acc132f42f243369299)
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---
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target/i386/tcg/decode-new.c.inc | 11 ++++++-----
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1 file changed, 6 insertions(+), 5 deletions(-)
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diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
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index 80c579164f..d5fd8d965c 100644
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--- a/target/i386/tcg/decode-new.c.inc
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+++ b/target/i386/tcg/decode-new.c.inc
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@@ -105,6 +105,7 @@
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#define vex3 .vex_class = 3,
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#define vex4 .vex_class = 4,
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#define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned,
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+#define vex4_rep5 .vex_class = 4, .vex_special = X86_VEX_REPScalar,
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#define vex5 .vex_class = 5,
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#define vex6 .vex_class = 6,
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#define vex7 .vex_class = 7,
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@@ -839,8 +840,8 @@ static const X86OpEntry opcodes_0F[256] = {
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[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
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[0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
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- [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
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- [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3),
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+ [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3),
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+ [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3),
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[0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */
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[0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */
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[0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
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@@ -878,7 +879,7 @@ static const X86OpEntry opcodes_0F[256] = {
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[0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
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[0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
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- [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex3 p_00_66_f3_f2),
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+ [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
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[0x5b] = X86_OP_GROUP0(0F5B),
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[0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
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[0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
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@@ -1447,9 +1448,9 @@ static bool validate_vex(DisasContext *s, X86DecodedInsn *decode)
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* Instructions which differ between 00/66 and F2/F3 in the
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* exception classification and the size of the memory operand.
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*/
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- assert(e->vex_class == 1 || e->vex_class == 2);
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+ assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4);
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if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) {
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- e->vex_class = 3;
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+ e->vex_class = e->vex_class < 4 ? 3 : 5;
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if (s->vex_l) {
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goto illegal;
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}
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--
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2.39.1
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