commit 61616f7ddaaef1b79df85f0a3e969c886604de6c Author: Heike Jagode Date: Mon Apr 2 17:47:31 2018 -0400 PAPI preset event support for Intel Knights Mill. diff --git a/src/papi_events.csv b/src/papi_events.csv index faa4ae2f5..bb11f61d3 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -851,8 +851,10 @@ PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD # # # Intel MIC / Xeon-Phi / Knights Landing +# Intel Knights Mill # CPU,knl +CPU,knm PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES @@ -885,6 +887,7 @@ PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED:JCC,BR_INST_RETIRED:TAKEN_JCC PRESET,PAPI_RES_STL,NOT_DERIVED,RS_FULL_STALL:ANY PRESET,PAPI_STL_ICY,NOT_DERIVED,NO_ALLOC_CYCLES:ANY # +# End of knl,knm list CPU,Intel Core2 CPU,Intel Core commit 85003c716d76eff47607fa0967537c6cf63d8348 Author: Steve Walk Date: Fri Jun 8 15:50:50 2018 -0400 enable Cavium ThunderX2 support diff --git a/src/papi_events.csv b/src/papi_events.csv index bb11f61d3..46827f180 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -1841,6 +1841,31 @@ PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL + +##################### +# ARM ThunderX2 # +##################### +CPU,arm_thunderx2 +# +PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED +PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES +PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC +PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC +PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED +PRESET,PAPI_LD_INS,NOT_DERIVED,LD_RETIRED +PRESET,PAPI_SR_INS,NOT_DERIVED,ST_RETIRED +PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE_RD,L1D_CACHE_WR +PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL +PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD +PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR +PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE +PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL +PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE +PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL +PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD +PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR +PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD + # CPU,mips_74k # commit 111d01df256f691c2a2d2e14028fa4ebc9e63bed Author: Vince Weaver Date: Tue Jan 22 17:09:29 2019 -0500 papi_events: add cascade lake X support diff --git a/src/papi_events.csv b/src/papi_events.csv index f5bcf1a46..009074449 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -724,9 +724,11 @@ CPU,hsw_ep CPU,bdw CPU,bdw_ep CPU,skl -CPU,skx # Note, libpfm4 treats Kaby Lake as just a form of skylake CPU,kbl +CPU,skx +# Note, libpfm4 treats Cascade Lake-X as just a form of skylake-X +CPU,clx PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:THREAD_P PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES commit d5a1a9ae2e4102e03063e76e242d4a3547cd5df3 Author: Vince Weaver Date: Wed Jan 23 16:58:10 2019 -0500 papi_events: the skylake events are actually split in two, make sure cascadelake gets both cases too diff --git a/src/papi_events.csv b/src/papi_events.csv index 009074449..361813847 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -832,6 +832,7 @@ PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH CPU,skl CPU,skx +CPU,clx # PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE # PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE @@ -849,7 +850,7 @@ PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ_UOPS_NOT_DELIVERED:CYCLES_0_UOPS_DELIV_CORE PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD -# End of hsw,bdw,skl list +# End of hsw,bdw,skl,clx list # # # Intel MIC / Xeon-Phi / Knights Landing commit c9d0702caf582179cf89f28d987a68e48b9af0e9 Author: Daniel Barry Date: Mon May 20 16:31:45 2019 -0400 I have added PAPI POWER9 event definitions for PAPI_L2_DCR, PAPI_L2_DCW, PAPI_BR_CN, PAPI_BR_NTK, PAPI_BR_UCN, and PAPI_BR_TKN. These events have been tested. Their patterns of behavior were measured during the execution of performance benchmarks on Summit's POWER9 processors. The patterns of behavior for the corresponding events on Intel Haswell processors were measured during the execution of the same performance benchmarks. The respective events from each architecture behave similarly. diff --git a/src/papi_events.csv b/src/papi_events.csv index 361813847..f658931ed 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -1588,6 +1588,8 @@ PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_CMPL PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS PRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS +PRESET,PAPI_L2_DCR,NOT_DERIVED,PM_DATA_FROM_L2 +PRESET,PAPI_L2_DCW,NOT_DERIVED,PM_L2_ST_HIT PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM @@ -1617,6 +1619,10 @@ PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_TAKEN_BR_MPRED_CMPL PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED +PRESET,PAPI_BR_CN,DERIVED_SUB,PM_BR_CMPL,PM_BR_UNCOND +PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|N2|-|,PM_BR_CMPL,PM_BR_UNCOND,PM_BR_TAKEN_CMPL +PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND +PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_CORECT_PRED_TAKEN_CMPL PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE # CPU,ultra12 commit 6440c5995a10db05959325b1192368734bfa7e5b Author: Carl Love Date: Wed Aug 14 07:52:50 2019 -0400 Per Carl Love, "The POWER9 event PM_BR_TAKEN_CMPL includes conditional and unconditional branches. The equation for event PAPI_BR_NTK should not include the event PM_BR_UNCOND as PM_BR_TAKEN_CMPL already counts unconditional branches. The POWER9 event PM_LD_REF_L1 includes hits and misses to the L1. Thus we should not be adding PM_LS_MISS_L1_ALT when calculating PAPI_LD_INS on POWER9." The definitions for these preset events were changed accordingly, and their patterns of behavior were measured during the execution of performance benchmarks on the IBM POWER9 processors on Summit. The patterns of behavior for the corresponding events on the Intel Skylake and Broadwell processors were measured during the execution of the same performance benchmarks. The respective events from each architecture behave similarly. In addition, the new definitions pass the PAPI validation tests. Signed-off-by: Daniel Barry diff --git a/src/papi_events.csv b/src/papi_events.csv index f658931ed..8df74866e 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -1613,14 +1613,14 @@ PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN -PRESET,PAPI_LD_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1_ALT +PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1 PRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_TAKEN_BR_MPRED_CMPL PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED PRESET,PAPI_BR_CN,DERIVED_SUB,PM_BR_CMPL,PM_BR_UNCOND -PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|N2|-|,PM_BR_CMPL,PM_BR_UNCOND,PM_BR_TAKEN_CMPL +PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|,PM_BR_CMPL,PM_BR_TAKEN_CMPL PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_CORECT_PRED_TAKEN_CMPL PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE commit 20890adcb59a1c1648cb70be65332c03a3781e1a Author: Anthony Castaldo Date: Thu Jan 16 16:43:51 2020 -0500 Added two machine types to papi_events.csv to be in line with libpfm4 update to support amd64_fam17h_zen1 and zen2. diff --git a/src/papi_events.csv b/src/papi_events.csv index 97446ad2c..8e96adfbd 100644 --- a/src/papi_events.csv +++ b/src/papi_events.csv @@ -396,6 +396,8 @@ PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE # # CPU,amd64_fam17h +CPU,amd64_fam17h_zen1 +CPU,amd64_fam17h_zen2 # PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT