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No commits in common. 'c9' and 'c10-beta' have entirely different histories.
@ -1 +1 @@
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SOURCES/v2.2.tar.gz
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SOURCES/v2.3.tar.gz
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@ -1 +1 @@
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c2fd2e31ad2a7d5e4fb2c5884e396c4ce2bbab60 SOURCES/v2.2.tar.gz
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e7f08bb2a29a841eca00aff37a14987c84de1b56 SOURCES/v2.3.tar.gz
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@ -0,0 +1,36 @@
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--- numatop-2.2/common/os/os_util.c 2021-09-08 04:29:54.000000000 +0200
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+++ numatop-2.2/common/os/os_util.c 2022-08-13 15:24:06.607330278 +0200
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@@ -387,12 +387,10 @@
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int len = strlen(str);
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boolean_t ret = B_FALSE;
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- if ((scopy = malloc(len + 1)) == NULL) {
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+ if ((scopy = strdup(str)) == NULL) {
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return (B_FALSE);
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}
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- strncpy(scopy, str, len);
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- scopy[len] = 0;
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cur = scopy;
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while (cur < (scopy + len)) {
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--- numatop-2.2/common/reg.c 2021-09-08 04:29:54.000000000 +0200
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+++ numatop-2.2/common/reg.c 2022-08-13 16:16:12.060462958 +0200
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@@ -240,7 +240,7 @@
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}
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if (len > 0) {
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- (void) mvwprintw(r->hdl, line, pos_x, content);
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+ (void) mvwprintw(r->hdl, line, pos_x, "%s", content);
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}
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if (r->mode != 0) {
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@@ -267,7 +267,7 @@
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}
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if (len > 0) {
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- (void) mvwprintw(r->hdl, line, pos_x, content);
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+ (void) mvwprintw(r->hdl, line, pos_x, "%s", content);
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}
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(void) wattroff(r->hdl, A_REVERSE | A_BOLD);
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@ -1,172 +0,0 @@
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From ffd83b3a7749b3601eec305b8b8f9f44c3f3fe80 Mon Sep 17 00:00:00 2001
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From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
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Date: Fri, 10 Jun 2022 16:19:24 +0800
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Subject: [PATCH] Initial support for SPR
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SPR has more CPUs, so it requires the system with its max open files should
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bigger than 1024. In many systems, the default max open files are 1024, the
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error can be " Fail to setup perf":
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# ulimit -n
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1024 <------the max open files are 1024
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# ./numatop
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NumaTOP is starting ...
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Fail to setup perf (probably permission denied)!
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Need enlarge the max open files:
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# ulimit -n 8192
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# ulimit -n
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8192 <------now the max open files are 8192
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Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
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---
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intel/include/skl.h | 4 ++++
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intel/include/types.h | 5 +++--
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intel/plat.c | 13 ++++++++++---
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intel/skl.c | 26 ++++++++++++++++++++++++++
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4 files changed, 43 insertions(+), 5 deletions(-)
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diff --git a/intel/include/skl.h b/intel/include/skl.h
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index 67c8939..7a8b8f2 100644
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--- a/intel/include/skl.h
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+++ b/intel/include/skl.h
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@@ -47,6 +47,10 @@ extern void icx_profiling_config(perf_count_id_t, struct _plat_event_config *);
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extern void icx_ll_config(struct _plat_event_config *);
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extern int icx_offcore_num(void);
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+extern void spr_profiling_config(perf_count_id_t, struct _plat_event_config *);
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+extern void spr_ll_config(struct _plat_event_config *);
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+extern int spr_offcore_num(void);
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+
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#ifdef __cplusplus
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}
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#endif
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diff --git a/intel/include/types.h b/intel/include/types.h
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index 85aa074..76c7ad3 100644
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--- a/intel/include/types.h
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+++ b/intel/include/types.h
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@@ -45,10 +45,11 @@ typedef enum {
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CPU_HSX,
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CPU_BDX,
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CPU_SKX,
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- CPU_ICX
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+ CPU_ICX,
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+ CPU_SPR
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} cpu_type_t;
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-#define CPU_TYPE_NUM 11
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+#define CPU_TYPE_NUM 12
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typedef enum {
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PERF_COUNT_INVALID = -1,
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diff --git a/intel/plat.c b/intel/plat.c
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index fed4f1e..abf3766 100644
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--- a/intel/plat.c
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+++ b/intel/plat.c
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@@ -49,7 +49,8 @@ s_plat_profiling_config[CPU_TYPE_NUM] = {
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snbep_profiling_config,
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bdw_profiling_config,
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skl_profiling_config,
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- icx_profiling_config
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+ icx_profiling_config,
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+ spr_profiling_config
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};
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pfn_plat_ll_config_t
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@@ -64,7 +65,8 @@ s_plat_ll_config[CPU_TYPE_NUM] = {
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snbep_ll_config,
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bdw_ll_config,
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skl_ll_config,
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- icx_ll_config
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+ icx_ll_config,
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+ spr_ll_config
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};
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pfn_plat_offcore_num_t
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@@ -79,7 +81,8 @@ s_plat_offcore_num[CPU_TYPE_NUM] = {
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snb_offcore_num,
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bdw_offcore_num,
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skl_offcore_num,
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- icx_offcore_num
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+ icx_offcore_num,
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+ spr_offcore_num
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};
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/* ARGSUSED */
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@@ -171,6 +174,9 @@ cpu_type_get(void)
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case 106:
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type = CPU_ICX;
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break;
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+ case 143:
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+ type = CPU_SPR;
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+ break;
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}
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}
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@@ -210,6 +216,7 @@ plat_detect(void)
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/* fall through */
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case CPU_SKX:
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case CPU_ICX:
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+ case CPU_SPR:
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ret = 0;
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s_cpu_type = cpu_type;
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break;
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diff --git a/intel/skl.c b/intel/skl.c
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index 9e30574..ace0833 100644
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--- a/intel/skl.c
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+++ b/intel/skl.c
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@@ -55,6 +55,14 @@ static plat_event_config_t s_icx_config[PERF_COUNT_NUM] = {
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{ PERF_TYPE_RAW, 0x01BB, 0x53, 0x104000001, "off_core_response_1" }
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};
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+static plat_event_config_t s_spr_config[PERF_COUNT_NUM] = {
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+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
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+ { PERF_TYPE_RAW, 0x012A, 0x53, 0x730000001, "off_core_response_0" },
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+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
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+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
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+ { PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, "off_core_response_1" }
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+};
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+
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static plat_event_config_t s_skl_ll = {
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PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, "mem_trans_retired.latency_above_threshold"
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};
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@@ -71,6 +79,12 @@ icx_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg)
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plat_config_get(perf_count_id, cfg, s_icx_config);
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}
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+void
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+spr_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg)
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+{
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+ plat_config_get(perf_count_id, cfg, s_spr_config);
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+}
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+
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void
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skl_ll_config(plat_event_config_t *cfg)
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{
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@@ -83,6 +97,12 @@ icx_ll_config(plat_event_config_t *cfg)
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skl_ll_config(cfg);
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}
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+void
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+spr_ll_config(plat_event_config_t *cfg)
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+{
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+ skl_ll_config(cfg);
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+}
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+
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int
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skl_offcore_num(void)
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{
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@@ -94,3 +114,9 @@ icx_offcore_num(void)
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{
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return skl_offcore_num();
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}
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+
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+int
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+spr_offcore_num(void)
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+{
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+ return skl_offcore_num();
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+}
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--
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2.31.1
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