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155 lines
5.6 KiB
155 lines
5.6 KiB
2 years ago
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From f39735be3c1157fdfa7dd5c781048a411ebe4dc5 Mon Sep 17 00:00:00 2001
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From: Dan Williams <dan.j.williams@intel.com>
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Date: Sun, 23 Jan 2022 16:53:34 -0800
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Subject: [PATCH 106/217] cxl/list: Add 'host' entries for port-like objects
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Add the device name of the "host" device for a given CXL port object. The
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kernel calls this the 'uport' attribute.
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Link: https://lore.kernel.org/r/164298561473.3021641.16508989603599026269.stgit@dwillia2-desk3.amr.corp.intel.com
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
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---
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Documentation/cxl/cxl-list.txt | 9 +++++++++
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Documentation/cxl/lib/libcxl.txt | 5 +++++
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cxl/json.c | 4 ++++
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cxl/lib/libcxl.c | 10 ++++++++++
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cxl/lib/libcxl.sym | 2 ++
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cxl/libcxl.h | 2 ++
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6 files changed, 32 insertions(+)
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diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt
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index d342da2..30b6161 100644
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--- a/Documentation/cxl/cxl-list.txt
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+++ b/Documentation/cxl/cxl-list.txt
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@@ -210,6 +210,15 @@ OPTIONS
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--endpoints::
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Include endpoint objects (CXL Memory Device decoders) in the
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listing.
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+----
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+# cxl list -E
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+[
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+ {
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+ "endpoint":"endpoint2",
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+ "host":"mem0"
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+ }
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+]
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+----
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-e::
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--endpoint::
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diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
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index eebab37..e4b372d 100644
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--- a/Documentation/cxl/lib/libcxl.txt
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+++ b/Documentation/cxl/lib/libcxl.txt
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@@ -178,6 +178,7 @@ struct cxl_port *cxl_port_get_next(struct cxl_port *port);
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struct cxl_port *cxl_port_get_parent(struct cxl_port *port);
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struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
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struct cxl_ctx *cxl_port_get_ctx(struct cxl_port *port);
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+const char *cxl_port_get_host(struct cxl_port *port);
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#define cxl_port_foreach(parent, port) \
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for (port = cxl_port_get_first(parent); port != NULL; \
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@@ -192,6 +193,9 @@ as a parent object retrievable via cxl_port_get_parent().
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The root port of a hiearchy can be retrieved via any port instance in
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that hierarchy via cxl_port_get_bus().
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+The host of a port is the corresponding device name of the PCIe Root
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+Port, or Switch Upstream Port with CXL capabilities.
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+
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=== PORT: Attributes
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----
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const char *cxl_port_get_devname(struct cxl_port *port);
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@@ -222,6 +226,7 @@ struct cxl_endpoint *cxl_endpoint_get_next(struct cxl_endpoint *endpoint);
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struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint);
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struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
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struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
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+const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint);
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#define cxl_endpoint_foreach(port, endpoint) \
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for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL; \
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diff --git a/cxl/json.c b/cxl/json.c
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index 08f6192..af3b4fe 100644
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--- a/cxl/json.c
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+++ b/cxl/json.c
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@@ -258,6 +258,10 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port,
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if (jobj)
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json_object_object_add(jport, name_key, jobj);
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+ jobj = json_object_new_string(cxl_port_get_host(port));
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+ if (jobj)
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+ json_object_object_add(jport, "host", jobj);
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+
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if (!cxl_port_is_enabled(port)) {
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jobj = json_object_new_string("disabled");
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if (jobj)
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diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
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index a25e715..5f48202 100644
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--- a/cxl/lib/libcxl.c
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+++ b/cxl/lib/libcxl.c
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@@ -626,6 +626,11 @@ CXL_EXPORT struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint)
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return &endpoint->port;
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}
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+CXL_EXPORT const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint)
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+{
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+ return cxl_port_get_host(&endpoint->port);
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+}
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+
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CXL_EXPORT int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint)
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{
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return cxl_port_is_enabled(&endpoint->port);
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@@ -744,6 +749,11 @@ CXL_EXPORT struct cxl_bus *cxl_port_get_bus(struct cxl_port *port)
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return bus;
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}
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+CXL_EXPORT const char *cxl_port_get_host(struct cxl_port *port)
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+{
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+ return devpath_to_devname(port->uport);
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+}
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+
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CXL_EXPORT int cxl_port_is_enabled(struct cxl_port *port)
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{
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struct cxl_ctx *ctx = cxl_port_get_ctx(port);
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diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
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index 7a51a0c..dc2863e 100644
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--- a/cxl/lib/libcxl.sym
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+++ b/cxl/lib/libcxl.sym
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@@ -95,6 +95,7 @@ global:
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cxl_port_to_bus;
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cxl_port_is_endpoint;
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cxl_port_get_bus;
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+ cxl_port_get_host;
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cxl_endpoint_get_first;
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cxl_endpoint_get_next;
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cxl_endpoint_get_devname;
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@@ -103,4 +104,5 @@ global:
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cxl_endpoint_is_enabled;
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cxl_endpoint_get_parent;
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cxl_endpoint_get_port;
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+ cxl_endpoint_get_host;
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} LIBCXL_1;
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diff --git a/cxl/libcxl.h b/cxl/libcxl.h
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index f6ba9a1..a60777e 100644
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--- a/cxl/libcxl.h
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+++ b/cxl/libcxl.h
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@@ -83,6 +83,7 @@ bool cxl_port_is_switch(struct cxl_port *port);
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struct cxl_bus *cxl_port_to_bus(struct cxl_port *port);
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bool cxl_port_is_endpoint(struct cxl_port *port);
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struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
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+const char *cxl_port_get_host(struct cxl_port *port);
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#define cxl_port_foreach(parent, port) \
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for (port = cxl_port_get_first(parent); port != NULL; \
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@@ -97,6 +98,7 @@ struct cxl_ctx *cxl_endpoint_get_ctx(struct cxl_endpoint *endpoint);
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int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint);
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struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
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struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
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+const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint);
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#define cxl_endpoint_foreach(port, endpoint) \
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for (endpoint = cxl_endpoint_get_first(port); endpoint != NULL; \
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--
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2.27.0
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