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274 lines
8.3 KiB
274 lines
8.3 KiB
From fe46e3c810d0c4267e9c4e7d097bb7205b5ca9b6 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:22 +0200
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Subject: [PATCH 008/142] wifi: rtw89: 8852b: add chip_ops to read phy cap
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit 134cf7c01517d5cfaab940cacbb41525659de5f6
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Author: Ping-Ke Shih <pkshih@realtek.com>
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Date: Wed Sep 28 16:43:35 2022 +0800
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wifi: rtw89: 8852b: add chip_ops to read phy cap
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This efuse region is to store PHY calibration, and it is a separated region
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from the region that stores MAC address. Then, use these data to configure
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via chip_ops::power_trim that is a calibration mechanism of TX power.
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20220928084336.34981-9-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/core.h | 4 +
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drivers/net/wireless/realtek/rtw89/rtw8852b.c | 184 ++++++++++++++++++++++++++
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2 files changed, 188 insertions(+)
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diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h
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index be39d2200e054..51af91b30fc4d 100644
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--- a/drivers/net/wireless/realtek/rtw89/core.h
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+++ b/drivers/net/wireless/realtek/rtw89/core.h
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@@ -84,6 +84,7 @@ enum rtw89_subband {
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RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
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RTW89_SUBBAND_NR,
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+ RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
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};
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enum rtw89_gain_offset {
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@@ -2196,6 +2197,7 @@ struct rtw89_sta {
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struct rtw89_efuse {
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bool valid;
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+ bool power_k_valid;
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u8 xtal_cap;
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u8 addr[ETH_ALEN];
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u8 rfe_type;
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@@ -3425,8 +3427,10 @@ struct rtw89_phy_bb_gain_info {
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struct rtw89_phy_efuse_gain {
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bool offset_valid;
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+ bool comp_valid;
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s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
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s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
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+ s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
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};
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struct rtw89_dev {
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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index b80102b1dd7fd..e9bcea35a72a2 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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@@ -123,6 +123,186 @@ static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
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return 0;
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}
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+static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map)
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+{
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+#define PWR_K_CHK_OFFSET 0x5E9
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+#define PWR_K_CHK_VALUE 0xAA
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+ u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr;
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+
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+ if (phycap_map[offset] == PWR_K_CHK_VALUE)
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+ rtwdev->efuse.power_k_valid = true;
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+}
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+
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+static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
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+{
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+ struct rtw89_tssi_info *tssi = &rtwdev->tssi;
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+ static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB};
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+ u32 addr = rtwdev->chip->phycap_addr;
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+ bool pg = false;
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+ u32 ofst;
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+ u8 i, j;
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+
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+ for (i = 0; i < RF_PATH_NUM_8852B; i++) {
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+ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
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+ /* addrs are in decreasing order */
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+ ofst = tssi_trim_addr[i] - addr - j;
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+ tssi->tssi_trim[i][j] = phycap_map[ofst];
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+
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+ if (phycap_map[ofst] != 0xff)
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+ pg = true;
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+ }
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+ }
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+
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+ if (!pg) {
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+ memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
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+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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+ "[TSSI][TRIM] no PG, set all trim info to 0\n");
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+ }
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+
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+ for (i = 0; i < RF_PATH_NUM_8852B; i++)
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+ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
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+ rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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+ "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
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+ i, j, tssi->tssi_trim[i][j],
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+ tssi_trim_addr[i] - j);
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+}
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+
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+static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
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+ u8 *phycap_map)
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+{
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+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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+ static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC};
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+ u32 addr = rtwdev->chip->phycap_addr;
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+ u8 i;
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+
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+ for (i = 0; i < RF_PATH_NUM_8852B; i++) {
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+ info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
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+
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
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+ i, info->thermal_trim[i]);
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+
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+ if (info->thermal_trim[i] != 0xff)
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+ info->pg_thermal_trim = true;
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+ }
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+}
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+
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+static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev)
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+{
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+#define __thm_setting(raw) \
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+({ \
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+ u8 __v = (raw); \
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+ ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
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+})
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+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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+ u8 i, val;
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+
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+ if (!info->pg_thermal_trim) {
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[THERMAL][TRIM] no PG, do nothing\n");
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+
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+ return;
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+ }
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+
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+ for (i = 0; i < RF_PATH_NUM_8852B; i++) {
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+ val = __thm_setting(info->thermal_trim[i]);
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+ rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
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+
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
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+ i, val);
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+ }
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+#undef __thm_setting
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+}
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+
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+static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
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+ u8 *phycap_map)
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+{
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+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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+ static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB};
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+ u32 addr = rtwdev->chip->phycap_addr;
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+ u8 i;
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+
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+ for (i = 0; i < RF_PATH_NUM_8852B; i++) {
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+ info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
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+
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
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+ i, info->pa_bias_trim[i]);
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+
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+ if (info->pa_bias_trim[i] != 0xff)
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+ info->pg_pa_bias_trim = true;
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+ }
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+}
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+
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+static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev)
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+{
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+ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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+ u8 pabias_2g, pabias_5g;
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+ u8 i;
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+
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+ if (!info->pg_pa_bias_trim) {
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[PA_BIAS][TRIM] no PG, do nothing\n");
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+
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+ return;
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+ }
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+
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+ for (i = 0; i < RF_PATH_NUM_8852B; i++) {
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+ pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
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+ pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
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+
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
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+ i, pabias_2g, pabias_5g);
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+
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+ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
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+ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
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+ }
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+}
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+
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+static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
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+{
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+ static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
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+ {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
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+ {0x590, 0x58F, 0, 0x58E, 0x58D},
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+ };
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+ struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
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+ u32 phycap_addr = rtwdev->chip->phycap_addr;
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+ bool valid = false;
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+ int path, i;
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+ u8 data;
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+
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+ for (path = 0; path < 2; path++)
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+ for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
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+ if (comp_addrs[path][i] == 0)
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+ continue;
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+
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+ data = phycap_map[comp_addrs[path][i] - phycap_addr];
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+ valid |= _decode_efuse_gain(data, NULL,
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+ &gain->comp[path][i]);
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+ }
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+
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+ gain->comp_valid = valid;
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+}
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+
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+static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
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+{
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+ rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map);
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+ rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map);
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+ rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
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+ rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
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+ rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map);
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+
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+ return 0;
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+}
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+
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+static void rtw8852b_power_trim(struct rtw89_dev *rtwdev)
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+{
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+ rtw8852b_thermal_trim(rtwdev);
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+ rtw8852b_pa_bias_trim(rtwdev);
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+}
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+
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static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, s16 ref)
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{
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@@ -369,6 +549,8 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.enable_bb_rf = rtw8852b_mac_enable_bb_rf,
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.disable_bb_rf = rtw8852b_mac_disable_bb_rf,
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.read_efuse = rtw8852b_read_efuse,
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+ .read_phycap = rtw8852b_read_phycap,
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+ .power_trim = rtw8852b_power_trim,
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.set_txpwr = rtw8852b_set_txpwr,
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.set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
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.init_txpwr_unit = rtw8852b_init_txpwr_unit,
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@@ -386,6 +568,8 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.limit_efuse_size = 1280,
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.dav_phy_efuse_size = 96,
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.dav_log_efuse_size = 16,
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+ .phycap_addr = 0x580,
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+ .phycap_size = 128,
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.dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
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BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
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BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
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--
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2.13.6
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