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336 lines
12 KiB
336 lines
12 KiB
From f655006252045c5f4009c8e9e5c82317d1a51d17 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:24 +0200
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Subject: [PATCH 025/142] wifi: rtw89: 8852b: add power on/off functions
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit b23b36efbdac603c491197dae1d27a3c5ac4b01c
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Author: Ping-Ke Shih <pkshih@realtek.com>
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Date: Sun Oct 9 20:53:56 2022 +0800
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wifi: rtw89: 8852b: add power on/off functions
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We need power on function to enable hardware circuits of MAC/BB/RF, and
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then download firmware and load PHY parameters. After more settings, it
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starts to work. When it enters idle, use power off function to have the
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lowest power consumption.
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20221009125403.19662-3-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/mac.h | 1 +
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drivers/net/wireless/realtek/rtw89/reg.h | 18 +++
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drivers/net/wireless/realtek/rtw89/rtw8852b.c | 192 ++++++++++++++++++++++++++
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3 files changed, 211 insertions(+)
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diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h
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index a9867ac351da7..a6cbafb75a2b8 100644
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--- a/drivers/net/wireless/realtek/rtw89/mac.h
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+++ b/drivers/net/wireless/realtek/rtw89/mac.h
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@@ -1014,6 +1014,7 @@ enum rtw89_mac_xtal_si_offset {
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#define XTAL_SI_PON_EI BIT(1)
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#define XTAL_SI_PON_WEI BIT(0)
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XTAL_SI_SRAM_CTRL = 0xA1,
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+#define XTAL_SI_SRAM_DIS BIT(1)
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#define FULL_BIT_MASK GENMASK(7, 0)
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};
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diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
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index 1539973296cd1..376ce7135b388 100644
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--- a/drivers/net/wireless/realtek/rtw89/reg.h
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+++ b/drivers/net/wireless/realtek/rtw89/reg.h
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@@ -34,6 +34,9 @@
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#define R_AX_SYS_CLK_CTRL 0x0008
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#define B_AX_CPU_CLK_EN BIT(14)
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+#define R_AX_SYS_SWR_CTRL1 0x0010
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+#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10)
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+
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#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
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#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
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#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
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@@ -42,6 +45,9 @@
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#define B_AX_R_DIS_PRST BIT(6)
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#define B_AX_WLOCK_1C_BIT6 BIT(5)
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+#define R_AX_AFE_LDO_CTRL 0x0020
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+#define B_AX_AON_OFF_PC_EN BIT(23)
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+
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#define R_AX_EFUSE_CTRL_1 0x0038
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#define B_AX_EF_PGPD_MASK GENMASK(30, 28)
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#define B_AX_EF_RDT BIT(27)
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@@ -118,6 +124,9 @@
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#define B_AX_R_AX_BG_LPF BIT(2)
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#define B_AX_R_AX_BG GENMASK(1, 0)
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+#define R_AX_HCI_LDO_CTRL 0x007A
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+#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0)
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+
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#define R_AX_PLATFORM_ENABLE 0x0088
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#define B_AX_AXIDMA_EN BIT(3)
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#define B_AX_WCPU_EN BIT(1)
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@@ -125,6 +134,7 @@
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#define R_AX_WLLPS_CTRL 0x0090
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#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
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+#define SW_LPS_OPTION 0x0001A0B2
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#define R_AX_SCOREBOARD 0x00AC
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#define B_AX_TOGGLE BIT(31)
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@@ -229,6 +239,9 @@
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#define R_AX_GPIO0_7_FUNC_SEL 0x02D0
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+#define R_AX_EECS_EESK_FUNC_SEL 0x02D8
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+#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4)
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+
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#define R_AX_LED1_FUNC_SEL 0x02DC
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#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
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#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1
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@@ -253,6 +266,10 @@
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#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
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#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
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+#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
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+#define B_AX_C3_L1_MASK GENMASK(5, 4)
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+#define B_AX_C1_L1_MASK GENMASK(1, 0)
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+
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#define R_AX_AFE_OFF_CTRL1 0x0444
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#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
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#define B_AX_S1_LDO2PWRCUT_F BIT(23)
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@@ -449,6 +466,7 @@
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#define B_AX_DISPATCHER_EN BIT(18)
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#define B_AX_BBRPT_EN BIT(17)
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#define B_AX_MAC_SEC_EN BIT(16)
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+#define B_AX_DMACREG_GCKEN BIT(15)
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#define B_AX_MAC_UN_EN BIT(15)
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#define B_AX_H_AXIDMA_EN BIT(14)
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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index af04a0284b560..f54a4ea3c6b53 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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@@ -56,6 +56,194 @@ static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
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NULL},
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};
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+static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
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+{
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+ u32 val32;
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+ u32 ret;
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+
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
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+ B_AX_AFSM_PCIE_SUS_EN);
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+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
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+ rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
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+
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+ ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
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+ 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
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+ ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN,
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+ 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
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+ rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
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+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
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+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
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+
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+ ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
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+ 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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+ rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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+ rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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+ rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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+
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+ rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
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+
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+ rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
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+
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
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+ XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
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+
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
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+ XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
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+ XTAL_SI_OFF_WEI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
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+ XTAL_SI_OFF_EI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
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+ XTAL_SI_PON_WEI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
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+ XTAL_SI_PON_EI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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+ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
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+
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+ fsleep(1000);
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+
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
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+ rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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+
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+ if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
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+ goto func_en;
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+
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+ rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
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+ rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
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+
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+ if (rtwdev->hal.cv == CHIP_CBV) {
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+ rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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+ rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
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+ rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
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+ }
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+
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+func_en:
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+ rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
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+ B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
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+ B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
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+ B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
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+ B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
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+ B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
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+ B_AX_DMACREG_GCKEN);
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+ rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
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+ B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
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+ B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
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+ B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
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+ B_AX_RMAC_EN);
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+
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+ rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
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+ PINMUX_EESK_FUNC_SEL_BT_LOG);
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+
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+ return 0;
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+}
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+
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+static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
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+{
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+ u32 val32;
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+ u32 ret;
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+
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
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+ XTAL_SI_RFC2RF);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
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+ XTAL_SI_SRAM2RFC);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
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+ if (ret)
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+ return ret;
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
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+ rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
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+
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
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+
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+ ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
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+
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+ ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
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+ 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
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+ if (ret)
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+ return ret;
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+
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+ rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
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+ rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
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+ rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
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+ rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
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+
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+ return 0;
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+}
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+
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static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse,
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struct rtw8852b_efuse *map)
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{
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@@ -1233,6 +1421,8 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.set_txpwr = rtw8852b_set_txpwr,
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.set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
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.init_txpwr_unit = rtw8852b_init_txpwr_unit,
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+ .pwr_on_func = rtw8852b_pwr_on_func,
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+ .pwr_off_func = rtw8852b_pwr_off_func,
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};
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const struct rtw89_chip_info rtw8852b_chip_info = {
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@@ -1242,6 +1432,8 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.dle_scc_rsvd_size = 98304,
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.hfc_param_ini = rtw8852b_hfc_param_ini_pcie,
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.dle_mem = rtw8852b_dle_mem_pcie,
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+ .pwr_on_seq = NULL,
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+ .pwr_off_seq = NULL,
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.sec_ctrl_efuse_size = 4,
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.physical_efuse_size = 1216,
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.logical_efuse_size = 2048,
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--
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2.13.6
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