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144 lines
5.4 KiB
144 lines
5.4 KiB
From fb633de5bb45947abf4265e9617d65b71203385c Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:24 +0200
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Subject: [PATCH 024/142] wifi: rtw89: 8852b: add chip_ops::set_channel_help
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit d0a95ef3ed86762d2356fd5443bebe7a6ef140c7
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Author: Ping-Ke Shih <pkshih@realtek.com>
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Date: Sun Oct 9 20:53:55 2022 +0800
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wifi: rtw89: 8852b: add chip_ops::set_channel_help
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This chip_ops is to assist set_channel, because we need setup and restore
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hardware before and after set_channel.
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Before set_channel, we stop transmitting, reset PPDU status, disable TSSI,
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and disable ADC. After set_channel, do opposite things in reverse order.
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20221009125403.19662-2-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/rtw8852b.c | 84 +++++++++++++++++++++++++++
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1 file changed, 84 insertions(+)
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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index b50fff00b1393..af04a0284b560 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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@@ -854,6 +854,30 @@ static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx p
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rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
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}
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+static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
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+ enum rtw89_phy_idx phy_idx, bool en)
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+{
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+ if (en) {
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+ rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
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+ B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
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+ rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
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+ B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
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+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
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+ if (band == RTW89_BAND_2G)
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+ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
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+ rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
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+ } else {
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+ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
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+ rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
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+ rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
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+ B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
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+ rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
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+ B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
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+ fsleep(1);
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+ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
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+ }
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+}
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+
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static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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@@ -897,6 +921,65 @@ static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
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rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
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}
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+static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
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+ enum rtw89_rf_path path)
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+{
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+ static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
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+ static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
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+
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+ if (en) {
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+ rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
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+ rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
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+ } else {
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+ rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
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+ rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
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+ }
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+}
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+
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+static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
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+ u8 phy_idx)
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+{
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+ if (!rtwdev->dbcc_en) {
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+ rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
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+ rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
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+ } else {
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+ if (phy_idx == RTW89_PHY_0)
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+ rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
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+ else
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+ rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
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+ }
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+}
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+
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+static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
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+{
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+ if (en)
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+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
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+ else
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+ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
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+}
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+
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+static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
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+ struct rtw89_channel_help_params *p,
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+ const struct rtw89_chan *chan,
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+ enum rtw89_mac_idx mac_idx,
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+ enum rtw89_phy_idx phy_idx)
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+{
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+ if (enter) {
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+ rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
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+ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
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+ rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
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+ rtw8852b_adc_en(rtwdev, false);
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+ fsleep(40);
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+ rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
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+ } else {
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+ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
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+ rtw8852b_adc_en(rtwdev, true);
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+ rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
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+ rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
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+ rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
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+ }
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+}
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+
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static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, s16 ref)
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{
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@@ -1143,6 +1226,7 @@ static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.enable_bb_rf = rtw8852b_mac_enable_bb_rf,
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.disable_bb_rf = rtw8852b_mac_disable_bb_rf,
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.set_channel = rtw8852b_set_channel,
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+ .set_channel_help = rtw8852b_set_channel_help,
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.read_efuse = rtw8852b_read_efuse,
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.read_phycap = rtw8852b_read_phycap,
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.power_trim = rtw8852b_power_trim,
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--
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2.13.6
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