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153 lines
5.2 KiB
153 lines
5.2 KiB
1 year ago
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From 9c5751f4eedd79a896915d7248106bb7e794b537 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:26 +0200
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Subject: [PATCH 035/142] wifi: rtw89: 8852b: rfk: add RX DCK
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit 212671074ab2f3e33fd5e95392c7356410ad7f8d
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Author: Ping-Ke Shih <pkshih@realtek.com>
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Date: Wed Oct 12 16:32:32 2022 +0800
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wifi: rtw89: 8852b: rfk: add RX DCK
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RX DCK is receiver DC calibration. With this calibration, we have proper
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DC offset to reflect correct received signal strength indicator. Do this
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calibration when bringing up interface and going to run on AP channel.
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20221012083234.20224-4-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c | 75 +++++++++++++++++++++++
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drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h | 1 +
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2 files changed, 76 insertions(+)
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
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index 1dcb900ef7007..306f6a292c59a 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.c
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@@ -12,6 +12,7 @@
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#include "rtw8852b_rfk_table.h"
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#include "rtw8852b_table.h"
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+#define RTW8852B_RXDCK_VER 0x1
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#define ADDC_T_AVG 100
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static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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@@ -32,6 +33,47 @@ static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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return val;
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}
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+static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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+ enum rtw89_rf_path path)
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+{
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+ rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);
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+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
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+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
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+ mdelay(1);
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+}
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+
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+static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
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+{
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+ u8 path, dck_tune;
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+ u32 rf_reg5;
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+
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, CV : 0x%x) ******\n",
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+ RTW8852B_RXDCK_VER, rtwdev->hal.cv);
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+
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+ for (path = 0; path < RF_PATH_NUM_8852B; path++) {
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+ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
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+ dck_tune = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE);
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+
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+ if (rtwdev->is_tssi_mode[path])
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+ rtw89_phy_write32_mask(rtwdev,
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+ R_P0_TSSI_TRK + (path << 13),
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+ B_P0_TSSI_TRK_EN, 0x1);
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+
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+ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
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+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0);
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+ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
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+ _set_rx_dck(rtwdev, phy, path);
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+ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune);
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+ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
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+
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+ if (rtwdev->is_tssi_mode[path])
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+ rtw89_phy_write32_mask(rtwdev,
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+ R_P0_TSSI_TRK + (path << 13),
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+ B_P0_TSSI_TRK_EN, 0x0);
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+ }
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+}
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+
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static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
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{
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u32 rf_reg5;
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@@ -488,6 +530,24 @@ static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
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rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
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}
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+static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
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+{
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+ u32 rf_mode;
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+ u8 path;
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+ int ret;
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+
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+ for (path = 0; path < RF_PATH_MAX; path++) {
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+ if (!(kpath & BIT(path)))
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+ continue;
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+
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+ ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode,
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+ rf_mode != 2, 2, 5000, false,
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+ rtwdev, path, RR_MOD, RR_MOD_MASK);
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+ rtw89_debug(rtwdev, RTW89_DBG_RFK,
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+ "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", path, ret);
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+ }
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+}
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+
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void rtw8852b_rck(struct rtw89_dev *rtwdev)
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{
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u8 path;
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@@ -505,6 +565,21 @@ void rtw8852b_dack(struct rtw89_dev *rtwdev)
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rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP);
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}
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+void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
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+{
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+ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0);
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+ u32 tx_en;
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+
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+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
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+ rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
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+ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
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+
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+ _rx_dck(rtwdev, phy_idx);
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+
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+ rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
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+ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
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+}
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+
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static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
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enum rtw89_bandwidth bw, bool dav)
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{
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h b/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h
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index 84325abc7f2c2..24e492484d274 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b_rfk.h
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@@ -9,6 +9,7 @@
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void rtw8852b_rck(struct rtw89_dev *rtwdev);
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void rtw8852b_dack(struct rtw89_dev *rtwdev);
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+void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
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void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
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const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx);
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--
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2.13.6
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