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136 lines
4.6 KiB
136 lines
4.6 KiB
1 year ago
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From 40c418f356774701b7ab0cfcab49677baf8bc3fd Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:34 +0200
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Subject: [PATCH 092/142] wifi: rtw89: 8852c: rfk: refine AGC tuning flow of
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DPK for irregular PA
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit ba1a6905c71898509fd3e8d1eb790b4e1213126f
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Author: Chih-Kang Chang <gary.chang@realtek.com>
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Date: Fri Dec 16 13:29:39 2022 +0800
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wifi: rtw89: 8852c: rfk: refine AGC tuning flow of DPK for irregular PA
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Some hardware modules don't have good RF characteristic as regular.
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It could have RF PA characteristic that current code doesn't handle
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properly, and it runs into wrong DPK flow that doesn't complete DPK
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resulting in bad EVM.
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Signed-off-by: Chih-Kang Chang <gary.chang@realtek.com>
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20221216052939.9991-1-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c | 38 ++++++++++++++++++-----
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1 file changed, 30 insertions(+), 8 deletions(-)
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
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index b0ea23d9f81fb..3c5fa3bb2a8f4 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c
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@@ -26,7 +26,7 @@ static const u32 rtw8852c_backup_bb_regs[] = {
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};
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static const u32 rtw8852c_backup_rf_regs[] = {
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- 0xdf, 0x8f, 0x97, 0xa3, 0x5, 0x10005
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+ 0xdf, 0x5f, 0x8f, 0x97, 0xa3, 0x5, 0x10005
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};
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#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852c_backup_bb_regs)
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@@ -1757,7 +1757,7 @@ u8 _rx_dck_channel_calc(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
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}
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#define RTW8852C_RF_REL_VERSION 34
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-#define RTW8852C_DPK_VER 0x10
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+#define RTW8852C_DPK_VER 0xf
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#define RTW8852C_DPK_TH_AVG_NUM 4
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#define RTW8852C_DPK_RF_PATH 2
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#define RTW8852C_DPK_KIP_REG_NUM 5
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@@ -1797,6 +1797,12 @@ enum dpk_agc_step {
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DPK_AGC_STEP_SET_TX_GAIN,
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};
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+enum dpk_pas_result {
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+ DPK_PAS_NOR,
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+ DPK_PAS_GT,
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+ DPK_PAS_LT,
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+};
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+
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static void _rf_direct_cntrl(struct rtw89_dev *rtwdev,
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enum rtw89_rf_path path, bool is_bybb)
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{
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@@ -2206,9 +2212,10 @@ static u8 _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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return _dpk_gainloss_read(rtwdev);
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}
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-static bool _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
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+static enum dpk_pas_result _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
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{
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u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
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+ u32 val1_sqrt_sum, val2_sqrt_sum;
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u8 i;
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rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
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@@ -2239,15 +2246,25 @@ static bool _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)
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}
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}
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- if (val1_i * val1_i + val1_q * val1_q >= (val2_i * val2_i + val2_q * val2_q) * 8 / 5)
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- return true;
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+ val1_sqrt_sum = val1_i * val1_i + val1_q * val1_q;
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+ val2_sqrt_sum = val2_i * val2_i + val2_q * val2_q;
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+
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+ if (val1_sqrt_sum < val2_sqrt_sum)
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+ return DPK_PAS_LT;
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+ else if (val1_sqrt_sum >= val2_sqrt_sum * 8 / 5)
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+ return DPK_PAS_GT;
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else
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- return false;
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+ return DPK_PAS_NOR;
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}
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static bool _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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enum rtw89_rf_path path, u8 kidx)
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{
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+ _dpk_kip_control_rfc(rtwdev, path, false);
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+ rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD,
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+ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
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+ _dpk_kip_control_rfc(rtwdev, path, true);
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+
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_dpk_one_shot(rtwdev, phy, path, D_RXAGC);
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return _dpk_sync_check(rtwdev, path, kidx);
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@@ -2285,6 +2302,7 @@ static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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u8 tmp_dbm = init_xdbm, tmp_gl_idx = 0;
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u8 tmp_rxbb;
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u8 goout = 0, agc_cnt = 0;
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+ enum dpk_pas_result pas;
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u16 dgain = 0;
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bool is_fail = false;
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int limit = 200;
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@@ -2320,9 +2338,13 @@ static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
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case DPK_AGC_STEP_GAIN_LOSS_IDX:
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tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx);
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+ pas = _dpk_pas_read(rtwdev, true);
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- if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) ||
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- tmp_gl_idx >= 7)
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+ if (pas == DPK_PAS_LT && tmp_gl_idx > 0)
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+ step = DPK_AGC_STEP_GL_LT_CRITERION;
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+ else if (pas == DPK_PAS_GT && tmp_gl_idx == 0)
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+ step = DPK_AGC_STEP_GL_GT_CRITERION;
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+ else if (tmp_gl_idx >= 7)
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step = DPK_AGC_STEP_GL_GT_CRITERION;
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else if (tmp_gl_idx == 0)
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step = DPK_AGC_STEP_GL_LT_CRITERION;
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--
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2.13.6
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