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94 lines
3.6 KiB
94 lines
3.6 KiB
1 year ago
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From e309aa380bd4b29305c760137b89bab98f920be5 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:24 +0200
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Subject: [PATCH 026/142] wifi: rtw89: 8852b: add basic baseband chip_ops
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit a804479839e1cf502a76c407f3e07135ddbe5032
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Author: Ping-Ke Shih <pkshih@realtek.com>
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Date: Sun Oct 9 20:53:57 2022 +0800
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wifi: rtw89: 8852b: add basic baseband chip_ops
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chip_ops::bb_reset is to reset baseband state after loading parameters,
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because its state could be unpredictable at that moment. The other is
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chip_ops::bb_sethw that is to set some baseband settings not including in
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parameter tables.
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20221009125403.19662-4-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/rtw8852b.c | 42 +++++++++++++++++++++++++++
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1 file changed, 42 insertions(+)
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diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852b.c b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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index f54a4ea3c6b53..f13c657f4d68d 100644
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--- a/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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+++ b/drivers/net/wireless/realtek/rtw89/rtw8852b.c
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@@ -1066,6 +1066,46 @@ static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
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}
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}
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+static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
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+ enum rtw89_phy_idx phy_idx)
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+{
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+ rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
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+ rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
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+ rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
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+ rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
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+ rtw8852b_bb_reset_all(rtwdev, phy_idx);
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+ rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
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+ rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
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+ rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
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+ rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
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+}
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+
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+static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
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+ enum rtw89_phy_idx phy_idx)
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+{
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+ u32 addr;
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+
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+ for (addr = R_AX_PWR_MACID_LMT_TABLE0;
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+ addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
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+ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
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+}
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+
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+static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev)
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+{
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+ struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
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+
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+ rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
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+ rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
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+
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+ rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
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+
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+ /* read these registers after loading BB parameters */
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+ gain->offset_base[RTW89_PHY_0] =
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+ rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
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+ gain->rssi_base[RTW89_PHY_0] =
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+ rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
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+}
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+
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static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
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enum rtw89_phy_idx phy_idx)
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{
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@@ -1413,6 +1453,8 @@ static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
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static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.enable_bb_rf = rtw8852b_mac_enable_bb_rf,
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.disable_bb_rf = rtw8852b_mac_disable_bb_rf,
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+ .bb_reset = rtw8852b_bb_reset,
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+ .bb_sethw = rtw8852b_bb_sethw,
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.set_channel = rtw8852b_set_channel,
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.set_channel_help = rtw8852b_set_channel_help,
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.read_efuse = rtw8852b_read_efuse,
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--
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2.13.6
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