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80 lines
3.0 KiB
80 lines
3.0 KiB
1 year ago
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From 096c34d9acbb90e410d5e31e1820fcddd513cdc3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= <ihuguet@redhat.com>
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Date: Wed, 24 May 2023 15:00:23 +0200
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Subject: [PATCH 018/142] wifi: rtw89: 8852b: set proper configuration before
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loading NCTL
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Bugzilla: https://bugzilla.redhat.com/2207499
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commit d0c820cc5bcf768598ca3e9f6e29f3e4e5589827
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Author: Ping-Ke Shih <pkshih@realtek.com>
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Date: Wed Oct 5 16:32:09 2022 +0800
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wifi: rtw89: 8852b: set proper configuration before loading NCTL
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Before loading RF NCTL table, we need to configure IQK/DPK clock and reset
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them, and then polling NCTL state ready. Since 8852BE needs additional
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one setting, add it by this patch. Also, give them proper names.
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Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
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Signed-off-by: Kalle Valo <kvalo@kernel.org>
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Link: https://lore.kernel.org/r/20221005083212.45683-4-pkshih@realtek.com
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Signed-off-by: Íñigo Huguet <ihuguet@redhat.com>
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---
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drivers/net/wireless/realtek/rtw89/phy.c | 12 +++++++-----
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drivers/net/wireless/realtek/rtw89/reg.h | 2 ++
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2 files changed, 9 insertions(+), 5 deletions(-)
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diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
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index 5645aeb2a8d08..2db1209e6cd35 100644
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--- a/drivers/net/wireless/realtek/rtw89/phy.c
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+++ b/drivers/net/wireless/realtek/rtw89/phy.c
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@@ -1368,13 +1368,15 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
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int ret;
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/* IQK/DPK clock & reset */
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- rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
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- rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
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- rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
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- rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
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+ rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
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+ rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
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+ rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
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+ rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
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+ if (chip->chip_id == RTL8852B)
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+ rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
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/* check 0x8080 */
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- rtw89_phy_write32(rtwdev, 0x8000, 0x8);
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+ rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
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ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
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1000, false, rtwdev);
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diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
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index 874cca85eaadf..82af17d7d8d31 100644
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--- a/drivers/net/wireless/realtek/rtw89/reg.h
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+++ b/drivers/net/wireless/realtek/rtw89/reg.h
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@@ -4039,6 +4039,7 @@
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#define B_P0_RFM_TX_OPT BIT(6)
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#define B_P0_RFM_BT_EN BIT(5)
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#define B_P0_RFM_OUT GENMASK(4, 0)
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+#define R_P0_PATH_RST 0x58AC
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#define R_P0_TXDPD 0x58D4
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#define B_P0_TXDPD GENMASK(31, 28)
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#define R_P0_TXPW_RSTB 0x58DC
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@@ -4083,6 +4084,7 @@
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#define R_P1_RFCTM 0x7864
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#define R_P1_RFCTM_RDY BIT(26)
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#define B_P1_RFCTM_VAL GENMASK(25, 20)
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+#define R_P1_PATH_RST 0x78AC
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#define R_P1_TXPW_RSTB 0x78DC
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#define B_P1_TXPW_RSTB_MANON BIT(30)
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#define B_P1_TXPW_RSTB_TSSI BIT(31)
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--
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2.13.6
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