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238 lines
6.2 KiB
238 lines
6.2 KiB
Index: src/drivers/ata/ahci.c
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===================================================================
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--- src.orig/drivers/ata/ahci.c 2023-08-05 22:17:36.154536550 +0200
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+++ src/drivers/ata/ahci.c 2023-08-05 22:44:46.371682515 +0200
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@@ -64,6 +64,7 @@
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enum board_ids {
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/* board IDs by feature in alphabetical order */
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board_ahci,
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+#if 0
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board_ahci_ign_iferr,
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board_ahci_mobile,
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board_ahci_nomsi,
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@@ -93,11 +94,13 @@
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board_ahci_mcp67 = board_ahci_mcp65,
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board_ahci_mcp73 = board_ahci_mcp65,
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board_ahci_mcp79 = board_ahci_mcp77,
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+#endif
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};
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static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static void ahci_remove_one(struct pci_dev *dev);
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static void ahci_shutdown_one(struct pci_dev *dev);
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+#if 0
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static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline);
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static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
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@@ -106,6 +109,7 @@
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static bool is_mcp89_apple(struct pci_dev *pdev);
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static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline);
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+#endif
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#ifdef CONFIG_PM
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static int ahci_pci_device_runtime_suspend(struct device *dev);
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static int ahci_pci_device_runtime_resume(struct device *dev);
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@@ -119,6 +123,7 @@
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AHCI_SHT(DRV_NAME),
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};
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+#if 0
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static struct ata_port_operations ahci_vt8251_ops = {
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.inherits = &ahci_ops,
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.hardreset = ahci_vt8251_hardreset,
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@@ -133,6 +138,7 @@
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.inherits = &ahci_ops,
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.hardreset = ahci_avn_hardreset,
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};
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+#endif
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static const struct ata_port_info ahci_port_info[] = {
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/* by features */
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@@ -142,6 +148,7 @@
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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+#if 0
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[board_ahci_ign_iferr] = {
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AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
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.flags = AHCI_FLAG_COMMON,
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@@ -257,9 +264,11 @@
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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},
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+#endif
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};
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static const struct pci_device_id ahci_pci_tbl[] = {
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+#if 0
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/* Intel */
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{ PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
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{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
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@@ -463,11 +472,13 @@
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/* AMD is using RAID class only for ahci controllers */
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{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
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+#endif
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/* Dell S140/S150 */
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
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PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
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+#if 0
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/* VIA */
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{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
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{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
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@@ -624,6 +635,7 @@
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/* Generic, PCI class code for AHCI */
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
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+#endif
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{ } /* terminate list */
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};
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@@ -709,6 +721,7 @@
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ahci_init_controller(host);
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}
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+#if 0
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static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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@@ -849,6 +862,7 @@
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DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
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return rc;
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}
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+#endif
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#ifdef CONFIG_PM
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@@ -913,9 +927,11 @@
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struct ata_host *host = pci_get_drvdata(pdev);
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int rc;
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+#if 0
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/* Apple BIOS helpfully mangles the registers on resume */
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if (is_mcp89_apple(pdev))
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ahci_mcp89_apple_enable(pdev);
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+#endif
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if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
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rc = ahci_reset_controller(host);
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@@ -973,6 +989,7 @@
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ahci_print_info(host, scc_s);
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}
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+#if 0
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/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
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* hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
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* support PMP and the 4726 either directly exports the device
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@@ -1477,6 +1494,7 @@
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}
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}
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}
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+#endif
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#ifdef CONFIG_ARM64
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/*
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@@ -1648,9 +1666,11 @@
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if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
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return;
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+#if 0
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/* Skip applying the quirk on Denverton and beyond */
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if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
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return;
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+#endif
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/*
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* port_map is determined from PORTS_IMPL PCI register which is
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@@ -1696,6 +1716,7 @@
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ata_print_version_once(&pdev->dev, DRV_VERSION);
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+#if 0
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/* The AHCI driver can only drive the SATA ports, the PATA driver
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can drive them all so if both drivers are selected make sure
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AHCI stays out of the way */
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@@ -1725,12 +1746,14 @@
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if (pdev->device == 0xa084)
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ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
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}
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+#endif
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/* acquire resources */
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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+#if 0
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == 0x2652 || pdev->device == 0x2653)) {
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u8 map;
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@@ -1746,6 +1769,7 @@
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return -ENODEV;
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}
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}
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+#endif
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/* AHCI controllers often implement SFF compatible interface.
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* Grab all PCI BARs just in case.
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@@ -1761,6 +1785,7 @@
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return -ENOMEM;
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hpriv->flags |= (unsigned long)pi.private_data;
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+#if 0
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/* MCP65 revision A1 and A2 can't do MSI */
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if (board_id == board_ahci_mcp65 &&
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(pdev->revision == 0xa1 || pdev->revision == 0xa2))
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@@ -1773,6 +1798,7 @@
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/* only some SB600s can do 64bit DMA */
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if (ahci_sb600_enable_64bit(pdev))
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hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
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+#endif
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hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
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@@ -1783,9 +1809,11 @@
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&dev_attr_remapped_nvme.attr,
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NULL);
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+#if 0
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/* must set flag prior to save config in order to take effect */
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if (ahci_broken_devslp(pdev))
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hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
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+#endif
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#ifdef CONFIG_ARM64
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if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
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@@ -1827,6 +1855,7 @@
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ahci_set_em_messages(hpriv, &pi);
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+#if 0
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if (ahci_broken_system_poweroff(pdev)) {
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pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
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dev_info(&pdev->dev,
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@@ -1854,6 +1883,7 @@
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/* Acer SA5-271 workaround modifies private_data */
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acer_sa5_271_workaround(hpriv, pdev);
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+#endif
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/* CAP.NP sometimes indicate the index of the last enabled
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* port, at other times, that of the last possible port, so
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@@ -1899,11 +1929,13 @@
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ap->ops = &ata_dummy_port_ops;
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}
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+#if 0
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/* apply workaround for ASUS P5W DH Deluxe mainboard */
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ahci_p5wdh_workaround(host);
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/* apply gtf filter quirk */
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ahci_gtf_filter_workaround(host);
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+#endif
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/* initialize adapter */
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rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
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