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81 lines
2.3 KiB
81 lines
2.3 KiB
2 years ago
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From 186092c6ba8825598ffdbf15dbf0823c771f560d Mon Sep 17 00:00:00 2001
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From: Wilco Dijkstra <wdijkstr@arm.com>
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Date: Tue, 10 Aug 2021 13:42:07 +0100
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Subject: [PATCH] [3/5] AArch64: Improve A64FX memset for remaining bytes
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Simplify handling of remaining bytes. Avoid lots of taken branches and complex
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whilelo computations, instead unconditionally write vectors from the end.
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Reviewed-by: Naohiro Tamura <naohirot@fujitsu.com>
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---
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sysdeps/aarch64/multiarch/memset_a64fx.S | 46 +++++++-----------------
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1 file changed, 13 insertions(+), 33 deletions(-)
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diff --git a/sysdeps/aarch64/multiarch/memset_a64fx.S b/sysdeps/aarch64/multiarch/memset_a64fx.S
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index 75cf43ae79..337c86be6f 100644
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--- a/sysdeps/aarch64/multiarch/memset_a64fx.S
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+++ b/sysdeps/aarch64/multiarch/memset_a64fx.S
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@@ -130,38 +130,19 @@ L(unroll8):
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b 1b
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L(last):
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- whilelo p0.b, xzr, rest
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- whilelo p1.b, vector_length, rest
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- b.last 1f
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- st1b z0.b, p0, [dst, #0, mul vl]
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- st1b z0.b, p1, [dst, #1, mul vl]
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- ret
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-1: lsl tmp1, vector_length, 1 // vector_length * 2
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- whilelo p2.b, tmp1, rest
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- incb tmp1
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- whilelo p3.b, tmp1, rest
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- b.last 1f
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- st1b z0.b, p0, [dst, #0, mul vl]
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- st1b z0.b, p1, [dst, #1, mul vl]
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- st1b z0.b, p2, [dst, #2, mul vl]
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- st1b z0.b, p3, [dst, #3, mul vl]
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- ret
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-1: lsl tmp1, vector_length, 2 // vector_length * 4
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- whilelo p4.b, tmp1, rest
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- incb tmp1
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- whilelo p5.b, tmp1, rest
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- incb tmp1
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- whilelo p6.b, tmp1, rest
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- incb tmp1
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- whilelo p7.b, tmp1, rest
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- st1b z0.b, p0, [dst, #0, mul vl]
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- st1b z0.b, p1, [dst, #1, mul vl]
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- st1b z0.b, p2, [dst, #2, mul vl]
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- st1b z0.b, p3, [dst, #3, mul vl]
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- st1b z0.b, p4, [dst, #4, mul vl]
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- st1b z0.b, p5, [dst, #5, mul vl]
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- st1b z0.b, p6, [dst, #6, mul vl]
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- st1b z0.b, p7, [dst, #7, mul vl]
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+ cmp count, vector_length, lsl 1
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+ b.ls 2f
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+ add tmp2, vector_length, vector_length, lsl 2
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+ cmp count, tmp2
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+ b.ls 5f
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+ st1b z0.b, p0, [dstend, -8, mul vl]
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+ st1b z0.b, p0, [dstend, -7, mul vl]
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+ st1b z0.b, p0, [dstend, -6, mul vl]
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+5: st1b z0.b, p0, [dstend, -5, mul vl]
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+ st1b z0.b, p0, [dstend, -4, mul vl]
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+ st1b z0.b, p0, [dstend, -3, mul vl]
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+2: st1b z0.b, p0, [dstend, -2, mul vl]
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+ st1b z0.b, p0, [dstend, -1, mul vl]
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ret
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L(L1_prefetch): // if rest >= L1_SIZE
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@@ -199,7 +180,6 @@ L(L2):
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subs count, count, CACHE_LINE_SIZE
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b.hi 1b
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add count, count, CACHE_LINE_SIZE
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- add dst, dst, CACHE_LINE_SIZE
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b L(last)
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END (MEMSET)
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--
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2.31.1
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