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137 lines
5.7 KiB
137 lines
5.7 KiB
9 months ago
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From 475b63702ef38b69558fc3d31a0b66776a70f1d3 Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Mon, 1 Nov 2021 00:49:52 -0500
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Subject: [PATCH] x86: Double size of ERMS rep_movsb_threshold in
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dl-cacheinfo.h
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Content-type: text/plain; charset=UTF-8
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No bug.
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This patch doubles the rep_movsb_threshold when using ERMS. Based on
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benchmarks the vector copy loop, especially now that it handles 4k
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aliasing, is better for these medium ranged.
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On Skylake with ERMS:
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Size, Align1, Align2, dst>src,(rep movsb) / (vec copy)
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4096, 0, 0, 0, 0.975
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4096, 0, 0, 1, 0.953
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4096, 12, 0, 0, 0.969
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4096, 12, 0, 1, 0.872
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4096, 44, 0, 0, 0.979
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4096, 44, 0, 1, 0.83
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4096, 0, 12, 0, 1.006
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4096, 0, 12, 1, 0.989
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4096, 0, 44, 0, 0.739
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4096, 0, 44, 1, 0.942
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4096, 12, 12, 0, 1.009
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4096, 12, 12, 1, 0.973
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4096, 44, 44, 0, 0.791
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4096, 44, 44, 1, 0.961
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4096, 2048, 0, 0, 0.978
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4096, 2048, 0, 1, 0.951
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4096, 2060, 0, 0, 0.986
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4096, 2060, 0, 1, 0.963
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4096, 2048, 12, 0, 0.971
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4096, 2048, 12, 1, 0.941
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4096, 2060, 12, 0, 0.977
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4096, 2060, 12, 1, 0.949
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8192, 0, 0, 0, 0.85
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8192, 0, 0, 1, 0.845
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8192, 13, 0, 0, 0.937
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8192, 13, 0, 1, 0.939
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8192, 45, 0, 0, 0.932
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8192, 45, 0, 1, 0.927
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8192, 0, 13, 0, 0.621
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8192, 0, 13, 1, 0.62
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8192, 0, 45, 0, 0.53
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8192, 0, 45, 1, 0.516
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8192, 13, 13, 0, 0.664
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8192, 13, 13, 1, 0.659
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8192, 45, 45, 0, 0.593
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8192, 45, 45, 1, 0.575
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8192, 2048, 0, 0, 0.854
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8192, 2048, 0, 1, 0.834
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8192, 2061, 0, 0, 0.863
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8192, 2061, 0, 1, 0.857
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8192, 2048, 13, 0, 0.63
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8192, 2048, 13, 1, 0.629
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8192, 2061, 13, 0, 0.627
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8192, 2061, 13, 1, 0.62
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Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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---
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sysdeps/x86/cacheinfo.h | 8 +++++---
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sysdeps/x86/dl-tunables.list | 26 +++++++++++++++-----------
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2 files changed, 20 insertions(+), 14 deletions(-)
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diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h
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index cc3941d3..ac025e08 100644
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--- a/sysdeps/x86/cacheinfo.h
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+++ b/sysdeps/x86/cacheinfo.h
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@@ -411,18 +411,20 @@ init_cacheinfo (void)
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/* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */
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unsigned int minimum_rep_movsb_threshold;
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- /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16). */
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+ /* NB: The default REP MOVSB threshold is 4096 * (VEC_SIZE / 16) for
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+ VEC_SIZE == 64 or 32. For VEC_SIZE == 16, the default REP MOVSB
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+ threshold is 2048 * (VEC_SIZE / 16). */
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unsigned int rep_movsb_threshold;
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F)
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&& !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512))
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{
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- rep_movsb_threshold = 2048 * (64 / 16);
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+ rep_movsb_threshold = 4096 * (64 / 16);
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minimum_rep_movsb_threshold = 64 * 8;
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}
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else if (CPU_FEATURE_PREFERRED_P (cpu_features,
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AVX_Fast_Unaligned_Load))
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{
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- rep_movsb_threshold = 2048 * (32 / 16);
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+ rep_movsb_threshold = 4096 * (32 / 16);
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minimum_rep_movsb_threshold = 32 * 8;
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}
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else
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diff --git a/sysdeps/x86/dl-tunables.list b/sysdeps/x86/dl-tunables.list
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index 89bf2966..56c6834a 100644
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--- a/sysdeps/x86/dl-tunables.list
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+++ b/sysdeps/x86/dl-tunables.list
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@@ -32,17 +32,21 @@ glibc {
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}
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x86_rep_movsb_threshold {
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type: SIZE_T
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- # Since there is overhead to set up REP MOVSB operation, REP MOVSB
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- # isn't faster on short data. The memcpy micro benchmark in glibc
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- # shows that 2KB is the approximate value above which REP MOVSB
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- # becomes faster than SSE2 optimization on processors with Enhanced
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- # REP MOVSB. Since larger register size can move more data with a
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- # single load and store, the threshold is higher with larger register
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- # size. Note: Since the REP MOVSB threshold must be greater than 8
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- # times of vector size and the default value is 2048 * (vector size
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- # / 16), the default value and the minimum value must be updated at
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- # run-time. NB: Don't set the default value since we can't tell if
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- # the tunable value is set by user or not [BZ #27069].
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+ # Since there is overhead to set up REP MOVSB operation, REP
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+ # MOVSB isn't faster on short data. The memcpy micro benchmark
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+ # in glibc shows that 2KB is the approximate value above which
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+ # REP MOVSB becomes faster than SSE2 optimization on processors
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+ # with Enhanced REP MOVSB. Since larger register size can move
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+ # more data with a single load and store, the threshold is
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+ # higher with larger register size. Micro benchmarks show AVX
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+ # REP MOVSB becomes faster apprximately at 8KB. The AVX512
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+ # threshold is extrapolated to 16KB. For machines with FSRM the
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+ # threshold is universally set at 2112 bytes. Note: Since the
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+ # REP MOVSB threshold must be greater than 8 times of vector
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+ # size and the default value is 4096 * (vector size / 16), the
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+ # default value and the minimum value must be updated at
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+ # run-time. NB: Don't set the default value since we can't tell
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+ # if the tunable value is set by user or not [BZ #27069].
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minval: 1
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}
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x86_rep_stosb_threshold {
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--
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GitLab
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