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175 lines
6.4 KiB
175 lines
6.4 KiB
9 months ago
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commit 3c1766ea10043f2e9625f3cba3bda37c84b32cf0
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Author: Paul A. Clarke <pc@us.ibm.com>
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Date: Thu Jul 18 19:37:13 2019 -0500
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[powerpc] fe{en,dis}ableexcept, fesetmode: optimize FPSCR accesses
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Since fe{en,dis}ableexcept() and fesetmode() read-modify-write just the
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"mode" (exception enable and rounding mode) bits of the Floating Point Status
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Control Register (FPSCR), the lighter weight 'mffsl' instruction can be used
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to read the FPSCR (enables and rounding mode), and 'mtfsf 0b00000011' can be
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used to write just those bits back to the FPSCR. The net is better performance.
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In addition, fe{en,dis}ableexcept() read the FPSCR again after writing it, or
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they determine that it doesn't need to be written because it is not changing.
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In either case, the local variable holds the current values of the enable
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bits in the FPSCR. This local variable can be used instead of again reading
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the FPSCR.
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Also, that value of the FPSCR which is read the second time is validated
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against the requested enables. Since the write can't fail, this validation
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step is unnecessary, and can be removed. Instead, the exceptions to be
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enabled (or disabled) are transformed into available bits in the FPSCR,
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then validated after being transformed back, to ensure that all requested
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bits are actually being set. For example, FE_INVALID_SQRT can be
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requested, but cannot actually be set. This bit is not mapped during the
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transformations, so a test for that bit being set before and after
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transformations will show the bit would not be set, and the function will
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return -1 for failure.
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Finally, convert the local macros in fesetmode.c to more generally useful
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macros in fenv_libc.h.
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diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
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index 90bc3d12c6d8558c..2a776c72fb5a2b70 100644
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--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
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+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
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@@ -26,23 +26,25 @@ fedisableexcept (int excepts)
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int result, new;
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/* Get current exception mask to return. */
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- fe.fenv = curr.fenv = fegetenv_register ();
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+ fe.fenv = curr.fenv = fegetenv_status ();
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result = fenv_reg_to_exceptions (fe.l);
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if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
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excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID;
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+ new = fenv_exceptions_to_reg (excepts);
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+
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+ if (fenv_reg_to_exceptions (new) != excepts)
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+ return -1;
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+
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/* Sets the new exception mask. */
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- fe.l &= ~ fenv_exceptions_to_reg (excepts);
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+ fe.l &= ~new;
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if (fe.l != curr.l)
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- fesetenv_register (fe.fenv);
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+ fesetenv_mode (fe.fenv);
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- new = __fegetexcept ();
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if (new == 0 && result != 0)
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(void)__fe_mask_env ();
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- if ((new & excepts) != 0)
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- result = -1;
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return result;
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}
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diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
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index e029971b9a460c28..6f5a828e80965bfa 100644
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--- a/sysdeps/powerpc/fpu/feenablxcpt.c
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+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
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@@ -26,24 +26,25 @@ feenableexcept (int excepts)
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int result, new;
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/* Get current exception mask to return. */
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- fe.fenv = curr.fenv = fegetenv_register ();
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+ fe.fenv = curr.fenv = fegetenv_status ();
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result = fenv_reg_to_exceptions (fe.l);
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if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
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excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID;
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+ new = fenv_exceptions_to_reg (excepts);
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+
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+ if (fenv_reg_to_exceptions (new) != excepts)
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+ return -1;
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+
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/* Sets the new exception mask. */
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- fe.l |= fenv_exceptions_to_reg (excepts);
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+ fe.l |= new;
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if (fe.l != curr.l)
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- fesetenv_register (fe.fenv);
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+ fesetenv_mode (fe.fenv);
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- new = __fegetexcept ();
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if (new != 0 && result == 0)
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(void) __fe_nomask_env_priv ();
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- if ((new & excepts) != excepts)
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- result = -1;
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-
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return result;
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}
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diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
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index f9634a64d186c076..b244770d115ea7bb 100644
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--- a/sysdeps/powerpc/fpu/fenv_libc.h
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+++ b/sysdeps/powerpc/fpu/fenv_libc.h
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@@ -71,6 +71,11 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
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asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
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} while(0)
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+/* Set the last 2 nibbles of the FPSCR, which contain the
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+ exception enables and the rounding mode.
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+ 'fegetenv_status' retrieves these bits by reading the FPSCR. */
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+#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env));
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+
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/* This very handy macro:
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- Sets the rounding mode to 'round to nearest';
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- Sets the processor into IEEE mode; and
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@@ -209,8 +214,11 @@ enum {
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(FPSCR_VE_MASK|FPSCR_OE_MASK|FPSCR_UE_MASK|FPSCR_ZE_MASK|FPSCR_XE_MASK)
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#define FPSCR_BASIC_EXCEPTIONS_MASK \
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(FPSCR_VX_MASK|FPSCR_OX_MASK|FPSCR_UX_MASK|FPSCR_ZX_MASK|FPSCR_XX_MASK)
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-
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+#define FPSCR_FPRF_MASK \
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+ (FPSCR_FPRF_C_MASK|FPSCR_FPRF_FL_MASK|FPSCR_FPRF_FG_MASK| \
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+ FPSCR_FPRF_FE_MASK|FPSCR_FPRF_FU_MASK)
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#define FPSCR_CONTROL_MASK (FPSCR_ENABLES_MASK|FPSCR_NI_MASK|FPSCR_RN_MASK)
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+#define FPSCR_STATUS_MASK (FPSCR_FR_MASK|FPSCR_FI_MASK|FPSCR_FPRF_MASK)
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/* The bits in the FENV(1) ABI for exceptions correspond one-to-one with bits
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in the FPSCR, albeit shifted to different but corresponding locations.
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diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c
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index 32203a24ff434a32..29e088d5ab1c0d93 100644
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--- a/sysdeps/powerpc/fpu/fesetmode.c
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+++ b/sysdeps/powerpc/fpu/fesetmode.c
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@@ -19,11 +19,6 @@
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#include <fenv_libc.h>
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#include <fpu_control.h>
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-#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \
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- | _FPU_MASK_XM | _FPU_MASK_IM)
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-
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-#define FPU_STATUS 0xbffff700ULL
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-
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int
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fesetmode (const femode_t *modep)
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{
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@@ -32,18 +27,18 @@ fesetmode (const femode_t *modep)
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/* Logic regarding enabled exceptions as in fesetenv. */
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new.fenv = *modep;
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- old.fenv = fegetenv_register ();
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- new.l = (new.l & ~FPU_STATUS) | (old.l & FPU_STATUS);
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+ old.fenv = fegetenv_status ();
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+ new.l = (new.l & ~FPSCR_STATUS_MASK) | (old.l & FPSCR_STATUS_MASK);
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if (old.l == new.l)
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return 0;
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- if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
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+ if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
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(void) __fe_nomask_env_priv ();
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- if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
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+ if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
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(void) __fe_mask_env ();
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- fesetenv_register (new.fenv);
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+ fesetenv_mode (new.fenv);
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return 0;
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}
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