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189 lines
5.8 KiB
189 lines
5.8 KiB
Description: Add arm64 support
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Author: Karel Gardas <karel.gardas@centrum.cz>
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Author: Colin Watson <cjwatson@ubuntu.com>
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Bug: https://ghc.haskell.org/trac/ghc/ticket/7942
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Last-Update: 2014-04-04
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Index: b/aclocal.m4
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===================================================================
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--- a/aclocal.m4
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+++ b/aclocal.m4
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@@ -173,7 +173,7 @@
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GET_ARM_ISA()
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test -z "[$]2" || eval "[$]2=\"ArchARM {armISA = \$ARM_ISA, armISAExt = \$ARM_ISA_EXT, armABI = \$ARM_ABI}\""
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;;
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- alpha|mips|mipseb|mipsel|hppa|hppa1_1|ia64|m68k|rs6000|s390|s390x|sparc64|vax)
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+ aarch64|alpha|mips|mipseb|mipsel|hppa|hppa1_1|ia64|m68k|rs6000|s390|s390x|sparc64|vax)
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test -z "[$]2" || eval "[$]2=ArchUnknown"
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;;
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*)
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@@ -1835,6 +1835,9 @@
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# converts cpu from gnu to ghc naming, and assigns the result to $target_var
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AC_DEFUN([GHC_CONVERT_CPU],[
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case "$1" in
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+ aarch64*)
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+ $2="aarch64"
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+ ;;
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alpha*)
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$2="alpha"
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;;
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Index: b/includes/stg/MachRegs.h
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===================================================================
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--- a/includes/stg/MachRegs.h
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+++ b/includes/stg/MachRegs.h
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@@ -43,6 +43,7 @@
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#define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
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#define sparc_REGS sparc_TARGET_ARCH
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#define arm_REGS arm_TARGET_ARCH
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+#define aarch64_REGS aarch64_TARGET_ARCH
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#define darwin_REGS darwin_TARGET_OS
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#else
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#define i386_REGS i386_HOST_ARCH
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@@ -50,6 +51,7 @@
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#define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
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#define sparc_REGS sparc_HOST_ARCH
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#define arm_REGS arm_HOST_ARCH
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+#define aarch64_REGS aarch64_HOST_ARCH
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#define darwin_REGS darwin_HOST_OS
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#endif
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@@ -461,6 +463,63 @@
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#endif /* arm */
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+/* -----------------------------------------------------------------------------
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+ The ARMv8/AArch64 ABI register mapping
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+
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+ The AArch64 provides 31 64-bit general purpose registers
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+ and 32 128-bit SIMD/floating point registers.
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+
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+ General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B)
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+
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+ Register | Special | Role in the procedure call standard
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+ ---------+---------+------------------------------------
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+ SP | | The Stack Pointer
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+ r30 | LR | The Link Register
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+ r29 | FP | The Frame Pointer
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+ r19-r28 | | Callee-saved registers
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+ r18 | | The Platform Register, if needed;
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+ | | or temporary register
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+ r17 | IP1 | The second intra-procedure-call temporary register
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+ r16 | IP0 | The first intra-procedure-call scratch register
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+ r9-r15 | | Temporary registers
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+ r8 | | Indirect result location register
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+ r0-r7 | | Parameter/result registers
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+
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+
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+ FPU/SIMD registers
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+
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+ s/d/q/v0-v7 Argument / result/ scratch registers
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+ s/d/q/v8-v15 callee-saved registers (must be preserved across subrutine calls,
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+ but only bottom 64-bit value needs to be preserved)
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+ s/d/q/v16-v31 temporary registers
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+
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+ ----------------------------------------------------------------------------- */
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+
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+#if aarch64_REGS
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+
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+#define REG(x) __asm__(#x)
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+
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+#define REG_Base r19
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+#define REG_Sp r20
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+#define REG_Hp r21
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+#define REG_R1 r22
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+#define REG_R2 r23
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+#define REG_R3 r24
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+#define REG_R4 r25
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+#define REG_R5 r26
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+#define REG_R6 r27
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+#define REG_SpLim r28
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+
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+#define REG_F1 s8
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+#define REG_F2 s9
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+#define REG_F3 s10
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+#define REG_F4 s11
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+
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+#define REG_D1 d12
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+#define REG_D2 d13
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+
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+#endif /* aarch64 */
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+
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#endif /* NO_REGS */
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/* -----------------------------------------------------------------------------
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Index: b/rts/StgCRun.c
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===================================================================
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--- a/rts/StgCRun.c
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+++ b/rts/StgCRun.c
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@@ -725,4 +725,70 @@
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}
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#endif
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+#ifdef aarch64_HOST_ARCH
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+
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+StgRegTable *
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+StgRun(StgFunPtr f, StgRegTable *basereg) {
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+ StgRegTable * r;
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+ __asm__ volatile (
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+ /*
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+ * save callee-saves registers on behalf of the STG code.
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+ */
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+ "stp x19, x20, [sp, #-16]!\n\t"
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+ "stp x21, x22, [sp, #-16]!\n\t"
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+ "stp x23, x24, [sp, #-16]!\n\t"
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+ "stp x25, x26, [sp, #-16]!\n\t"
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+ "stp x27, x28, [sp, #-16]!\n\t"
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+ "stp ip0, ip1, [sp, #-16]!\n\t"
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+ "str lr, [sp, #-8]!\n\t"
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+
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+ /*
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+ * allocate some space for Stg machine's temporary storage.
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+ * Note: RESERVER_C_STACK_BYTES has to be a round number here or
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+ * the assembler can't assemble it.
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+ */
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+ "str lr, [sp, %3]"
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+ /* "sub sp, sp, %3\n\t" */
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+ /*
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+ * Set BaseReg
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+ */
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+ "mov x19, %2\n\t"
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+ /*
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+ * Jump to function argument.
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+ */
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+ "bx %1\n\t"
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+
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+ ".globl " STG_RETURN "\n\t"
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+ ".type " STG_RETURN ", %%function\n"
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+ STG_RETURN ":\n\t"
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+ /*
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+ * Free the space we allocated
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+ */
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+ "ldr lr, [sp], %3\n\t"
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+ /* "add sp, sp, %3\n\t" */
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+ /*
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+ * Return the new register table, taking it from Stg's R1 (ARM64's R22).
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+ */
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+ "mov %0, x22\n\t"
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+ /*
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+ * restore callee-saves registers.
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+ */
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+ "ldr lr, [sp], #8\n\t"
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+ "ldp ip0, ip1, [sp], #16\n\t"
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+ "ldp x27, x28, [sp], #16\n\t"
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+ "ldp x25, x26, [sp], #16\n\t"
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+ "ldp x23, x24, [sp], #16\n\t"
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+ "ldp x21, x22, [sp], #16\n\t"
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+ "ldp x19, x20, [sp], #16\n\t"
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+
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+ : "=r" (r)
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+ : "r" (f), "r" (basereg), "i" (RESERVED_C_STACK_BYTES)
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+ : "%x19", "%x20", "%x21", "%x22", "%x23", "%x24", "%x25", "%x26", "%x27", "%x28",
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+ "%ip0", "%ip1", "%lr"
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+ );
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+ return r;
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+}
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+
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+#endif
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+
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#endif /* !USE_MINIINTERPRETER */
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