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@ -1,23 +1,27 @@
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Description: Add arm64 support
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Author: Karel Gardas <karel.gardas@centrum.cz>
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Author: Colin Watson <cjwatson@ubuntu.com>
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commit c29bf984dd20431cd4344e8a5c444d7a5be08389
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Author: Colin Watson <cjwatson@debian.org>
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Date: Mon Apr 21 22:26:56 2014 -0500
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Bug: https://ghc.haskell.org/trac/ghc/ticket/7942
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Last-Update: 2014-04-04
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Index: b/aclocal.m4
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ghc: initial AArch64 patches
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Signed-off-by: Austin Seipp <austin@well-typed.com>
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Index: ghc-7.8.3/aclocal.m4
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===================================================================
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--- a/aclocal.m4
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+++ b/aclocal.m4
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@@ -173,7 +173,7 @@
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--- ghc-7.8.3.orig/aclocal.m4 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/aclocal.m4 2014-07-10 10:16:42.529187516 +0200
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@@ -197,6 +197,9 @@
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GET_ARM_ISA()
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test -z "[$]2" || eval "[$]2=\"ArchARM {armISA = \$ARM_ISA, armISAExt = \$ARM_ISA_EXT, armABI = \$ARM_ABI}\""
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;;
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- alpha|mips|mipseb|mipsel|hppa|hppa1_1|ia64|m68k|rs6000|s390|s390x|sparc64|vax)
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+ aarch64|alpha|mips|mipseb|mipsel|hppa|hppa1_1|ia64|m68k|rs6000|s390|s390x|sparc64|vax)
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test -z "[$]2" || eval "[$]2=ArchUnknown"
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+ aarch64)
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+ test -z "[$]2" || eval "[$]2=ArchARM64"
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+ ;;
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alpha)
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test -z "[$]2" || eval "[$]2=ArchAlpha"
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;;
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*)
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@@ -1835,6 +1835,9 @@
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@@ -1862,6 +1865,9 @@
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# converts cpu from gnu to ghc naming, and assigns the result to $target_var
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AC_DEFUN([GHC_CONVERT_CPU],[
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case "$1" in
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@ -27,29 +31,161 @@ Index: b/aclocal.m4
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alpha*)
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$2="alpha"
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;;
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Index: b/includes/stg/MachRegs.h
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Index: ghc-7.8.3/compiler/nativeGen/AsmCodeGen.lhs
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===================================================================
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--- a/includes/stg/MachRegs.h
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+++ b/includes/stg/MachRegs.h
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@@ -43,6 +43,7 @@
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#define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
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#define sparc_REGS sparc_TARGET_ARCH
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#define arm_REGS arm_TARGET_ARCH
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+#define aarch64_REGS aarch64_TARGET_ARCH
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#define darwin_REGS darwin_TARGET_OS
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#else
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#define i386_REGS i386_HOST_ARCH
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@@ -50,6 +51,7 @@
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#define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
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#define sparc_REGS sparc_HOST_ARCH
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#define arm_REGS arm_HOST_ARCH
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+#define aarch64_REGS aarch64_HOST_ARCH
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#define darwin_REGS darwin_HOST_OS
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#endif
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@@ -461,6 +463,63 @@
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--- ghc-7.8.3.orig/compiler/nativeGen/AsmCodeGen.lhs 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/compiler/nativeGen/AsmCodeGen.lhs 2014-07-10 10:16:42.529187516 +0200
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@@ -166,6 +166,7 @@
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ArchPPC -> nCG' (ppcNcgImpl dflags)
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ArchSPARC -> nCG' (sparcNcgImpl dflags)
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ArchARM {} -> panic "nativeCodeGen: No NCG for ARM"
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+ ArchARM64 -> panic "nativeCodeGen: No NCG for ARM64"
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ArchPPC_64 -> panic "nativeCodeGen: No NCG for PPC 64"
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ArchAlpha -> panic "nativeCodeGen: No NCG for Alpha"
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ArchMipseb -> panic "nativeCodeGen: No NCG for mipseb"
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Index: ghc-7.8.3/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs
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===================================================================
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--- ghc-7.8.3.orig/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs 2014-07-10 10:16:42.529187516 +0200
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@@ -113,6 +113,7 @@
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ArchSPARC -> 14
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ArchPPC_64 -> panic "trivColorable ArchPPC_64"
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ArchARM _ _ _ -> panic "trivColorable ArchARM"
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+ ArchARM64 -> panic "trivColorable ArchARM64"
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ArchAlpha -> panic "trivColorable ArchAlpha"
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ArchMipseb -> panic "trivColorable ArchMipseb"
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ArchMipsel -> panic "trivColorable ArchMipsel"
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@@ -137,6 +138,7 @@
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ArchSPARC -> 22
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ArchPPC_64 -> panic "trivColorable ArchPPC_64"
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ArchARM _ _ _ -> panic "trivColorable ArchARM"
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+ ArchARM64 -> panic "trivColorable ArchARM64"
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ArchAlpha -> panic "trivColorable ArchAlpha"
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ArchMipseb -> panic "trivColorable ArchMipseb"
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ArchMipsel -> panic "trivColorable ArchMipsel"
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@@ -161,6 +163,7 @@
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ArchSPARC -> 11
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ArchPPC_64 -> panic "trivColorable ArchPPC_64"
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ArchARM _ _ _ -> panic "trivColorable ArchARM"
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+ ArchARM64 -> panic "trivColorable ArchARM64"
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ArchAlpha -> panic "trivColorable ArchAlpha"
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ArchMipseb -> panic "trivColorable ArchMipseb"
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ArchMipsel -> panic "trivColorable ArchMipsel"
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@@ -185,6 +188,7 @@
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ArchSPARC -> 0
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ArchPPC_64 -> panic "trivColorable ArchPPC_64"
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ArchARM _ _ _ -> panic "trivColorable ArchARM"
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+ ArchARM64 -> panic "trivColorable ArchARM64"
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ArchAlpha -> panic "trivColorable ArchAlpha"
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ArchMipseb -> panic "trivColorable ArchMipseb"
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ArchMipsel -> panic "trivColorable ArchMipsel"
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Index: ghc-7.8.3/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs
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===================================================================
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--- ghc-7.8.3.orig/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs 2014-07-10 10:16:42.529187516 +0200
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@@ -74,6 +74,7 @@
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ArchPPC -> PPC.Instr.maxSpillSlots dflags
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ArchSPARC -> SPARC.Instr.maxSpillSlots dflags
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ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
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+ ArchARM64 -> panic "maxSpillSlots ArchARM64"
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ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64"
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ArchAlpha -> panic "maxSpillSlots ArchAlpha"
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ArchMipseb -> panic "maxSpillSlots ArchMipseb"
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Index: ghc-7.8.3/compiler/nativeGen/RegAlloc/Linear/Main.hs
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===================================================================
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--- ghc-7.8.3.orig/compiler/nativeGen/RegAlloc/Linear/Main.hs 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/compiler/nativeGen/RegAlloc/Linear/Main.hs 2014-07-10 10:16:42.529187516 +0200
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@@ -207,6 +207,7 @@
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ArchSPARC -> linearRegAlloc' dflags (frInitFreeRegs platform :: SPARC.FreeRegs) first_id block_live sccs
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ArchPPC -> linearRegAlloc' dflags (frInitFreeRegs platform :: PPC.FreeRegs) first_id block_live sccs
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ArchARM _ _ _ -> panic "linearRegAlloc ArchARM"
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+ ArchARM64 -> panic "linearRegAlloc ArchARM64"
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ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64"
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ArchAlpha -> panic "linearRegAlloc ArchAlpha"
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ArchMipseb -> panic "linearRegAlloc ArchMipseb"
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Index: ghc-7.8.3/compiler/nativeGen/TargetReg.hs
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===================================================================
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--- ghc-7.8.3.orig/compiler/nativeGen/TargetReg.hs 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/compiler/nativeGen/TargetReg.hs 2014-07-10 10:16:42.529187516 +0200
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@@ -54,6 +54,7 @@
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ArchSPARC -> SPARC.virtualRegSqueeze
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ArchPPC_64 -> panic "targetVirtualRegSqueeze ArchPPC_64"
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ArchARM _ _ _ -> panic "targetVirtualRegSqueeze ArchARM"
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+ ArchARM64 -> panic "targetVirtualRegSqueeze ArchARM64"
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ArchAlpha -> panic "targetVirtualRegSqueeze ArchAlpha"
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ArchMipseb -> panic "targetVirtualRegSqueeze ArchMipseb"
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ArchMipsel -> panic "targetVirtualRegSqueeze ArchMipsel"
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@@ -70,6 +71,7 @@
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ArchSPARC -> SPARC.realRegSqueeze
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ArchPPC_64 -> panic "targetRealRegSqueeze ArchPPC_64"
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ArchARM _ _ _ -> panic "targetRealRegSqueeze ArchARM"
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+ ArchARM64 -> panic "targetRealRegSqueeze ArchARM64"
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ArchAlpha -> panic "targetRealRegSqueeze ArchAlpha"
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ArchMipseb -> panic "targetRealRegSqueeze ArchMipseb"
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ArchMipsel -> panic "targetRealRegSqueeze ArchMipsel"
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@@ -85,6 +87,7 @@
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ArchSPARC -> SPARC.classOfRealReg
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ArchPPC_64 -> panic "targetClassOfRealReg ArchPPC_64"
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ArchARM _ _ _ -> panic "targetClassOfRealReg ArchARM"
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+ ArchARM64 -> panic "targetClassOfRealReg ArchARM64"
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ArchAlpha -> panic "targetClassOfRealReg ArchAlpha"
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ArchMipseb -> panic "targetClassOfRealReg ArchMipseb"
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ArchMipsel -> panic "targetClassOfRealReg ArchMipsel"
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@@ -100,6 +103,7 @@
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ArchSPARC -> SPARC.mkVirtualReg
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ArchPPC_64 -> panic "targetMkVirtualReg ArchPPC_64"
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ArchARM _ _ _ -> panic "targetMkVirtualReg ArchARM"
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+ ArchARM64 -> panic "targetMkVirtualReg ArchARM64"
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ArchAlpha -> panic "targetMkVirtualReg ArchAlpha"
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ArchMipseb -> panic "targetMkVirtualReg ArchMipseb"
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ArchMipsel -> panic "targetMkVirtualReg ArchMipsel"
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@@ -115,6 +119,7 @@
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ArchSPARC -> SPARC.regDotColor
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ArchPPC_64 -> panic "targetRegDotColor ArchPPC_64"
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ArchARM _ _ _ -> panic "targetRegDotColor ArchARM"
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+ ArchARM64 -> panic "targetRegDotColor ArchARM64"
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ArchAlpha -> panic "targetRegDotColor ArchAlpha"
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ArchMipseb -> panic "targetRegDotColor ArchMipseb"
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ArchMipsel -> panic "targetRegDotColor ArchMipsel"
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Index: ghc-7.8.3/compiler/utils/Platform.hs
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===================================================================
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--- ghc-7.8.3.orig/compiler/utils/Platform.hs 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/compiler/utils/Platform.hs 2014-07-10 10:16:42.529187516 +0200
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@@ -52,6 +52,7 @@
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, armISAExt :: [ArmISAExt]
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, armABI :: ArmABI
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}
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+ | ArchARM64
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| ArchAlpha
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| ArchMipseb
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| ArchMipsel
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Index: ghc-7.8.3/includes/stg/HaskellMachRegs.h
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===================================================================
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--- ghc-7.8.3.orig/includes/stg/HaskellMachRegs.h 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/includes/stg/HaskellMachRegs.h 2014-07-10 10:16:42.533187516 +0200
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@@ -38,6 +38,7 @@
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#define MACHREGS_powerpc (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
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#define MACHREGS_sparc sparc_TARGET_ARCH
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#define MACHREGS_arm arm_TARGET_ARCH
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+#define MACHREGS_aarch64 aarch64_TARGET_ARCH
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#define MACHREGS_darwin darwin_TARGET_OS
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#endif /* arm */
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#endif
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Index: ghc-7.8.3/includes/stg/MachRegs.h
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===================================================================
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--- ghc-7.8.3.orig/includes/stg/MachRegs.h 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/includes/stg/MachRegs.h 2014-07-10 10:16:42.533187516 +0200
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@@ -1,6 +1,6 @@
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/* -----------------------------------------------------------------------------
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*
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- * (c) The GHC Team, 1998-2011
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+ * (c) The GHC Team, 1998-2014
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*
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* Registers used in STG code. Might or might not correspond to
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* actual machine registers.
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@@ -531,6 +531,61 @@
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#define REG_D2 d11
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#endif
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+/* -----------------------------------------------------------------------------
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+ The ARMv8/AArch64 ABI register mapping
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@ -83,7 +219,7 @@ Index: b/includes/stg/MachRegs.h
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+
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+ ----------------------------------------------------------------------------- */
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+
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+#if aarch64_REGS
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+#elif MACHREGS_aarch64
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+
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+#define REG(x) __asm__(#x)
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+
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@ -106,16 +242,14 @@ Index: b/includes/stg/MachRegs.h
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+#define REG_D1 d12
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+#define REG_D2 d13
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+
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+#endif /* aarch64 */
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+
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#endif /* NO_REGS */
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#else
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/* -----------------------------------------------------------------------------
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Index: b/rts/StgCRun.c
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#error Cannot find platform to give register info for
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Index: ghc-7.8.3/rts/StgCRun.c
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===================================================================
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--- a/rts/StgCRun.c
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+++ b/rts/StgCRun.c
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@@ -725,4 +725,70 @@
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--- ghc-7.8.3.orig/rts/StgCRun.c 2014-07-10 10:16:42.533187516 +0200
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+++ ghc-7.8.3/rts/StgCRun.c 2014-07-10 10:16:42.533187516 +0200
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@@ -748,4 +748,70 @@
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}
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#endif
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