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634 lines
22 KiB
634 lines
22 KiB
From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Keith Seitz <keiths@redhat.com>
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Date: Thu, 6 May 2021 14:53:00 -0400
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Subject: gdb-rhbz1870031-p10-prefixed-insn-2of3.patch
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;; Backport "gdb-power10-single-step"
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;; (Will Schmidt, RHBZ 1870031)
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commit c8a379440e0f8bf94ed5730e823c9256e64bf37c
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Author: Will Schmidt <will_schmidt@vnet.ibm.com>
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Date: Mon Apr 12 14:11:02 2021 -0500
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[PATCH] gdb-power10-single-step
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Hi,
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This is based on a patch originally written by Alan Modra.
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Powerpc / Power10 ISA 3.1 adds prefixed instructions, which
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are 8 bytes in length. This is in contrast to powerpc previously
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always having 4 byte instruction length. This patch implements
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changes to allow GDB to better detect prefixed instructions, and
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handle single stepping across the 8 byte instructions.
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Added #defines to help test for PNOP and prefix instructions.
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Update ppc_displaced_step_copy_insn() to handle pnop and prefixed
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instructions whem R=0 (non-pc-relative).
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Updated ppc_displaced_step_fixup() to properly handle the offset
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value matching the current instruction size
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Updated the for-loop within ppc_deal_with_atomic_sequence() to
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count instructions properly in case we have a mix of 4-byte and
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8-byte instructions within the atomic_sequence_length.
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Added testcase and harness to exercise pc-relative load/store
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instructions with R=0.
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2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com>
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gdb/ChangeLog:
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* rs6000-tdep.c: Add support for single-stepping of
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prefixed instructions.
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gdb/testsuite/ChangeLog:
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* gdb.arch/powerpc-plxv-nonrel.s: Testcase using
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non-relative plxv instructions.
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* gdb.arch/powerpc-plxv-nonrel.exp: Testcase harness.
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diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
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--- a/gdb/rs6000-tdep.c
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+++ b/gdb/rs6000-tdep.c
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@@ -814,7 +814,7 @@ typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
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rs6000_breakpoint;
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/* Instruction masks for displaced stepping. */
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-#define BRANCH_MASK 0xfc000000
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+#define OP_MASK 0xfc000000
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#define BP_MASK 0xFC0007FE
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#define B_INSN 0x48000000
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#define BC_INSN 0x40000000
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@@ -842,6 +842,11 @@ typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
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#define ADDPCIS_TARGET_REGISTER 0x03F00000
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#define ADDPCIS_INSN_REGSHIFT 21
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+#define PNOP_MASK 0xfff3ffff
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+#define PNOP_INSN 0x07000000
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+#define R_MASK 0x00100000
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+#define R_ZERO 0x00000000
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+
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/* Check if insn is one of the Load And Reserve instructions used for atomic
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sequences. */
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#define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
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@@ -873,10 +878,38 @@ ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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int insn;
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- read_memory (from, buf, len);
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+ len = target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY, NULL,
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+ buf, from, len);
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+ if ((ssize_t) len < PPC_INSN_SIZE)
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+ memory_error (TARGET_XFER_E_IO, from);
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insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
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+ /* Check for PNOP and for prefixed instructions with R=0. Those
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+ instructions are safe to displace. Prefixed instructions with R=1
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+ will read/write data to/from locations relative to the current PC.
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+ We would not be able to fixup after an instruction has written data
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+ into a displaced location, so decline to displace those instructions. */
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+ if ((insn & OP_MASK) == 1 << 26)
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+ {
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+ if (((insn & PNOP_MASK) != PNOP_INSN)
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+ && ((insn & R_MASK) != R_ZERO))
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+ {
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+ fprintf_unfiltered (gdb_stdlog,
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+ "displaced: {ppc} Not displacing prefixed "
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+ "instruction %08x at %s",
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+ insn, paddress (gdbarch, from));
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+ return NULL;
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+ }
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+ }
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+ else
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+ /* Non-prefixed instructions.. */
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+ {
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+ /* Set the instruction length to 4 to match the actual instruction
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+ length. */
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+ len = 4;
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+ }
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+
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/* Assume all atomic sequences start with a Load and Reserve instruction. */
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if (IS_LOAD_AND_RESERVE_INSN (insn))
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{
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@@ -917,11 +950,17 @@ ppc_displaced_step_fixup (struct gdbarch *gdbarch,
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ppc_displaced_step_closure *closure = (ppc_displaced_step_closure *) closure_;
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ULONGEST insn = extract_unsigned_integer (closure->buf.data (),
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PPC_INSN_SIZE, byte_order);
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- ULONGEST opcode = 0;
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+ ULONGEST opcode;
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/* Offset for non PC-relative instructions. */
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- LONGEST offset = PPC_INSN_SIZE;
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+ LONGEST offset;
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- opcode = insn & BRANCH_MASK;
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+ opcode = insn & OP_MASK;
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+
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+ /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
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+ if ((opcode) == 1 << 26)
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+ offset = 2 * PPC_INSN_SIZE;
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+ else
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+ offset = PPC_INSN_SIZE;
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if (debug_displaced)
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fprintf_unfiltered (gdb_stdlog,
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@@ -1058,13 +1097,16 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
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instructions. */
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for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
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{
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- loc += PPC_INSN_SIZE;
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+ if ((insn & OP_MASK) == 1 << 26)
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+ loc += 2 * PPC_INSN_SIZE;
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+ else
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+ loc += PPC_INSN_SIZE;
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insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
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/* Assume that there is at most one conditional branch in the atomic
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sequence. If a conditional branch is found, put a breakpoint in
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its destination address. */
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- if ((insn & BRANCH_MASK) == BC_INSN)
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+ if ((insn & OP_MASK) == BC_INSN)
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{
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int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
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int absolute = insn & 2;
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@@ -7095,7 +7137,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_displaced_step_location (gdbarch,
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displaced_step_at_entry_point);
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- set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
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+ set_gdbarch_max_insn_length (gdbarch, 2 * PPC_INSN_SIZE);
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/* Hook in ABI-specific overrides, if they have been registered. */
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info.target_desc = tdesc;
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diff --git a/gdb/testsuite/gdb.arch/powerpc-addpcis.exp b/gdb/testsuite/gdb.arch/powerpc-addpcis.exp
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-addpcis.exp
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@@ -0,0 +1,104 @@
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+# Copyright 2021 Free Software Foundation, Inc.
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+
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+# This program is free software; you can redistribute it and/or modify
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+# it under the terms of the GNU General Public License as published by
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+# the Free Software Foundation; either version 3 of the License, or
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+# (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
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+
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+# Test to confirm that gdb is properly single stepping over the
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+# displaced addpcis instruction.
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+# The addpcis instruction and its extended mnemonics lnia and subpcis
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+# apply an immediate shifted value (X || 0x0000) to the current PC/NIA
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+# value, and store that value into the instructions target register.
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+# When the instruction is displaced, it needs special handling.
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+
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+# lnia Rx == addpcis Rx,0
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+# subcis Rx,value == addpcis Rx,-value
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+
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+if { ![istarget powerpc*-*] } {
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+ verbose "Skipping powerpc addpcis test."
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+ return
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+}
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+
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+set retval 0
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+
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+standard_testfile .s
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+
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+if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
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+ {debug quiet}] } {
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+ return -1
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+}
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+
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+if ![runto_main] then {
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+ return
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+}
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+
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+set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
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+set bp1 *$check_pc+4
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+set bp2 *$check_pc+12
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+set bp3 *$check_pc+16
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+gdb_breakpoint $bp1
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+gdb_breakpoint $bp2
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+gdb_breakpoint $bp3
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+
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+gdb_test "stepi" "" "set r3 "
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+set check_r3 [get_hexadecimal_valueof "\$r3" "default0"]
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+gdb_test "stepi" "" "set r4"
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+set check_r4 [get_hexadecimal_valueof "\$r4" "default0"]
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+gdb_test "stepi" "" "set r5"
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+set check_r5 [get_hexadecimal_valueof "\$r5" "default0"]
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+gdb_test "stepi" "" "set r6"
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+set check_r6 [get_hexadecimal_valueof "\$r6" "default0"]
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+gdb_test "stepi" "" "set r7"
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+set check_r7 [get_hexadecimal_valueof "\$r7" "default0"]
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+gdb_test "stepi" "" "set r8"
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+set check_r8 [get_hexadecimal_valueof "\$r8" "default0"]
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+gdb_test "stepi" "" "set r9"
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+set check_r9 [get_hexadecimal_valueof "\$r9" "default0"]
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+
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+# R6 will contain the reference value. All other
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+# instructions in this test will be storing values
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+# relative to what is stored in R6.
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+
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+# subpcis 3,+0x100 # /* set r3 */
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+# subpcis 4,+0x10 # /* set r4 */
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+# subpcis 5,+0x1 # /* set r5 */
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+# lnia 6 # /* set r6 */
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+# addpcis 7,+0x1 # /* set r7 */
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+# addpcis 8,+0x10 # /* set r8 */
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+# addpcis 9,+0x100 # /* set r9 */
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+
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+if [expr $check_r3 + 0x1000000 != $check_r6 - 0xc ] {
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+ fail "unexpected value r3 + 0x1,000,000 != r6 + 0xc ; r3: $check_r3 r6: $check_r6 "
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+}
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+if [expr $check_r4 + 0x100000 != $check_r6 - 0x8 ] {
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+ fail "unexpected value r4 + 0x100,000 != r6 - 0x8 ; r4: $check_r4 r6: $check_r6 "
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+}
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+if [expr $check_r5 + 0x10000 != $check_r6 - 0x4 ] {
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+ fail "unexpected value r5 + 0x10,000 != r6 , r5: $check_r5 r6: $check_r6 "
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+}
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+if [expr $check_r6 != $check_r6] {
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+ fail "unexpected value r6 != r6 , r6: $check_r6 r6: $check_r6 "
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+}
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+if [expr $check_r7 - 0x10000 != $check_r6 + 0x4] {
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+ fail "unexpected value r7 - 0x10,000 != r6 + 0x4 , r7: $check_r7 r7: $check_r6 "
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+}
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+if [expr $check_r8 - 0x100000 != $check_r6 + 0x8 ] {
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+ fail "unexpected value r8 - 0x100,000 != r6 , r8: $check_r8 r8: $check_r6 "
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+}
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+if [expr $check_r9 - 0x1000000 != $check_r6 + 0xc ] {
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+ fail "unexpected value r9 - 0x1,000,000 != r6 + 0xc , r9: $check_r9 r6: $check_r6 "
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+}
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+
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+gdb_test "info break"
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+gdb_test "info register r3 r4 r5 r6 r7 r8 r9"
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+gdb_test "disas main"
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diff --git a/gdb/testsuite/gdb.arch/powerpc-addpcis.s b/gdb/testsuite/gdb.arch/powerpc-addpcis.s
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-addpcis.s
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@@ -0,0 +1,33 @@
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+/* This testcase is part of GDB, the GNU debugger.
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+
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+ Copyright 2021 Free Software Foundation, Inc.
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 3 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
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+
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+
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+/* Test to confirm that gdb is properly single stepping over the
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+ displaced addpcis instruction. */
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+
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+.global main
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+.type main,function
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+# addpcis: the sum of NIA + ( D || 0x0000) is placed in RT.
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+main:
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+ subpcis 3,+0x100 # /* set r3 */
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+ subpcis 4,+0x10 # /* set r4 */
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+ subpcis 5,+0x1 # /* set r5 */
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+ lnia 6 # /* set r6 */
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+ addpcis 7,+0x1 # /* set r7 */
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+ addpcis 8,+0x10 # /* set r8 */
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+ addpcis 9,+0x100 # /* set r9 */
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+ blr
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diff --git a/gdb/testsuite/gdb.arch/powerpc-lnia.exp b/gdb/testsuite/gdb.arch/powerpc-lnia.exp
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/powerpc-lnia.exp
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@@ -0,0 +1,100 @@
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+# Copyright 2021 Free Software Foundation, Inc.
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+
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+# This program is free software; you can redistribute it and/or modify
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+# it under the terms of the GNU General Public License as published by
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+# the Free Software Foundation; either version 3 of the License, or
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+# (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
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+# Test to see if gdb is properly single stepping over the
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+# displaced lnia instruction. This test checks that a series
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+# of lnia instructions are loading ascending values as expected.
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+
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+# lnia is an extended mnemonic for the addpcis instruction, which
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+# stores the $NIA plus an immediate value into a register.
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+#
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+# lnia Rx == addpcis Rx,0 == lnia Rx
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+# subcis Rx,value == addpcis Rx,-value
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+
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+if { ![istarget powerpc*-*] } {
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+ verbose "Skipping powerpc lnia test."
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+ return
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+}
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+
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+set retval 0
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+
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+standard_testfile .s
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+
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+if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
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+ {debug quiet}] } {
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+ return -1
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+}
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+
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+if ![runto_main] then {
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+ return
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+}
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+
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+set before_pc 0
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+set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
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+
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+# set some breakpoints on the instructions below main().
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+set bp1 *$check_pc+4
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+set bp2 *$check_pc+12
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+set bp3 *$check_pc+16
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+gdb_breakpoint $bp1
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+gdb_breakpoint $bp2
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+gdb_breakpoint $bp3
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+
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+# single-step through the lnia instructions, and retrieve the
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+# register values as we proceed.
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+gdb_test "stepi" "" "set r3"
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+set check_r3 [get_hexadecimal_valueof "\$r3" "default0"]
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+gdb_test "stepi" "" "set r4"
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+set check_r4 [get_hexadecimal_valueof "\$r4" "default0"]
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+gdb_test "stepi" "" "set r5"
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+set check_r5 [get_hexadecimal_valueof "\$r5" "default0"]
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+gdb_test "stepi" "" "set r6"
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+set check_r6 [get_hexadecimal_valueof "\$r6" "default0"]
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+gdb_test "stepi" "" "set r7"
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+set check_r7 [get_hexadecimal_valueof "\$r7" "default0"]
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+gdb_test "stepi" "" "set r8"
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+set check_r8 [get_hexadecimal_valueof "\$r8" "default0"]
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+gdb_test "stepi" "" "set r9"
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+set check_r9 [get_hexadecimal_valueof "\$r9" "default0"]
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+
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+# Ensure that our register values are as expected.
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+# Specifically that the values loaded by the lnia instruction
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+# reflect the value of the PC as if the instruction was
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+# not displaced.
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+if [expr $check_r3 + 4 != $check_r4] {
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+ fail "unexpected value r3+4 != r4 , r3: $check_r3 r4: $check_r4 "
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+}
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+if [expr $check_r4 + 4 != $check_r5] {
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+ fail "unexpected value r4+4 != r5 , r4: $check_r4 r5: $check_r5 "
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+}
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+if [expr $check_r5 + 4 != $check_r6] {
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+ fail "unexpected value r5+4 != r6 , r5: $check_r5 r6: $check_r6 "
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+}
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+if [expr $check_r6 + 4 != $check_r7] {
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+ fail "unexpected value r6+4 != r7 , r6: $check_r6 r7: $check_r7 "
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+}
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+if [expr $check_r7 + 4 != $check_r8] {
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+ fail "unexpected value r7+4 != r8 , r7: $check_r7 r8: $check_r8 "
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+}
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+if [expr $check_r8 + 4 != $check_r9] {
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+ fail "unexpected value r8+4 != r9 , r8: $check_r8 r9: $check_r9 "
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+}
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+
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+gdb_test "info break"
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|
+gdb_test "info register r3 r4 r5 r6 r7 r8 r9"
|
|
+gdb_test "disas main"
|
|
+
|
|
+# Let the inferior store all vector registers in a buffer, then dump
|
|
+# the buffer and check it.
|
|
diff --git a/gdb/testsuite/gdb.arch/powerpc-lnia.s b/gdb/testsuite/gdb.arch/powerpc-lnia.s
|
|
new file mode 100644
|
|
--- /dev/null
|
|
+++ b/gdb/testsuite/gdb.arch/powerpc-lnia.s
|
|
@@ -0,0 +1,32 @@
|
|
+/* This testcase is part of GDB, the GNU debugger.
|
|
+
|
|
+ Copyright 2021 Free Software Foundation, Inc.
|
|
+
|
|
+ This program is free software; you can redistribute it and/or modify
|
|
+ it under the terms of the GNU General Public License as published by
|
|
+ the Free Software Foundation; either version 3 of the License, or
|
|
+ (at your option) any later version.
|
|
+
|
|
+ This program is distributed in the hope that it will be useful,
|
|
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ GNU General Public License for more details.
|
|
+
|
|
+ You should have received a copy of the GNU General Public License
|
|
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
|
+
|
|
+/* Test to confirm that gdb properly handles lnia instructions
|
|
+ that load the current PC into a target register when executed
|
|
+ from a displaced location. */
|
|
+
|
|
+.global main
|
|
+.type main,function
|
|
+main:
|
|
+ lnia 3 # /* set r3 */
|
|
+ lnia 4 # /* set r4 */
|
|
+ lnia 5 # /* set r5 */
|
|
+ lnia 6 # /* set r6 */
|
|
+ lnia 7 # /* set r7 */
|
|
+ lnia 8 # /* set r8 */
|
|
+ lnia 9 # /* set r9 */
|
|
+ blr
|
|
diff --git a/gdb/testsuite/gdb.arch/powerpc-plxv-nonrel.exp b/gdb/testsuite/gdb.arch/powerpc-plxv-nonrel.exp
|
|
new file mode 100644
|
|
--- /dev/null
|
|
+++ b/gdb/testsuite/gdb.arch/powerpc-plxv-nonrel.exp
|
|
@@ -0,0 +1,130 @@
|
|
+# Copyright 2021 Free Software Foundation, Inc.
|
|
+
|
|
+# This program is free software; you can redistribute it and/or modify
|
|
+# it under the terms of the GNU General Public License as published by
|
|
+# the Free Software Foundation; either version 3 of the License, or
|
|
+# (at your option) any later version.
|
|
+#
|
|
+# This program is distributed in the hope that it will be useful,
|
|
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+# GNU General Public License for more details.
|
|
+#
|
|
+# You should have received a copy of the GNU General Public License
|
|
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+
|
|
+# Test to see if gdb is properly single stepping over the
|
|
+# displaced plxv instruction.
|
|
+
|
|
+if { ![istarget powerpc*-*] } {
|
|
+ verbose "Skipping powerpc plxv test."
|
|
+ return
|
|
+}
|
|
+
|
|
+set retval 0
|
|
+
|
|
+standard_testfile .s
|
|
+
|
|
+if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
|
|
+ {debug quiet}] } {
|
|
+ return -1
|
|
+}
|
|
+
|
|
+gdb_test "set radix 0b10000"
|
|
+gdb_test "set debug displaced"
|
|
+
|
|
+if ![runto_main] then {
|
|
+ return
|
|
+}
|
|
+
|
|
+gdb_test "set debug displaced on"
|
|
+
|
|
+# Proc to extract the uint128 hex value from the output of
|
|
+# a print vector statement.
|
|
+proc get_vector_hexadecimal_valueof { exp default {test ""} } {
|
|
+ set val "0x0000"
|
|
+ global gdb_prompt
|
|
+ if {$test == ""} {
|
|
+ set test "get vector_hexadecimal valueof \"${exp}\""
|
|
+ }
|
|
+ gdb_test_multiple "print $${exp}.uint128" $test {
|
|
+ -re -wrap "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*" {
|
|
+ set val $expect_out(1,string)
|
|
+ pass "$test"
|
|
+ }
|
|
+ -re -wrap ".*Illegal instruction.* $" {
|
|
+ fail "Illegal instruction on print."
|
|
+ set val 0xffff
|
|
+ }
|
|
+ }
|
|
+ return ${val}
|
|
+}
|
|
+
|
|
+# Proc to do a single-step, and ensure we gently handle
|
|
+# an illegal instruction situation.
|
|
+proc stepi_over_instruction { xyz } {
|
|
+ global gdb_prompt
|
|
+ gdb_test_multiple "stepi" "${xyz} " {
|
|
+ -re -wrap ".*Illegal instruction.*" {
|
|
+ fail "Illegal instruction on single step."
|
|
+ return
|
|
+ }
|
|
+ -re -wrap ".*" {
|
|
+ pass "stepi ${xyz}"
|
|
+ }
|
|
+ }
|
|
+}
|
|
+
|
|
+set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
|
|
+
|
|
+# set some breakpoints on the instructions below main().
|
|
+gdb_test "disas /r main"
|
|
+set bp1 *$check_pc+4
|
|
+set bp2 *$check_pc+0d12
|
|
+set bp3 *$check_pc+0d20
|
|
+set bp4 *$check_pc+0d28
|
|
+gdb_breakpoint $bp1
|
|
+gdb_breakpoint $bp2
|
|
+gdb_breakpoint $bp3
|
|
+gdb_breakpoint $bp4
|
|
+
|
|
+# single-step through the plxv instructions, and retrieve the
|
|
+# register values as we proceed.
|
|
+
|
|
+stepi_over_instruction "stepi over NOP"
|
|
+stepi_over_instruction "stepi over lnia"
|
|
+stepi_over_instruction "stepi over addi"
|
|
+
|
|
+stepi_over_instruction "stepi over vs4 assignment"
|
|
+set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"]
|
|
+
|
|
+stepi_over_instruction "stepi over vs5 assignment"
|
|
+set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"]
|
|
+
|
|
+stepi_over_instruction "stepi over vs6 assignment"
|
|
+set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"]
|
|
+
|
|
+stepi_over_instruction "stepi over vs7 assignment"
|
|
+set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"]
|
|
+
|
|
+set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2
|
|
+set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4
|
|
+set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6
|
|
+set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8
|
|
+
|
|
+if [expr $check_vs4 != $vs4_expected] {
|
|
+ fail "unexpected value vs4; actual:$check_vs4 expected:$vs4_expected"
|
|
+}
|
|
+if [expr $check_vs5 != $vs5_expected ] {
|
|
+ fail "unexpected value vs5; actual:$check_vs5 expected:$vs5_expected"
|
|
+}
|
|
+if [expr $check_vs6 != $vs6_expected ] {
|
|
+ fail "unexpected value vs6; actual:$check_vs6 expected:$vs6_expected"
|
|
+}
|
|
+if [expr $check_vs7 != $vs7_expected ] {
|
|
+ fail "unexpected value vs7; actual:$check_vs7 expected:$vs7_expected"
|
|
+}
|
|
+
|
|
+gdb_test "info break"
|
|
+gdb_test "info register vs4 vs5 vs6 vs7 "
|
|
+gdb_test "disas main #2"
|
|
diff --git a/gdb/testsuite/gdb.arch/powerpc-plxv-nonrel.s b/gdb/testsuite/gdb.arch/powerpc-plxv-nonrel.s
|
|
new file mode 100644
|
|
--- /dev/null
|
|
+++ b/gdb/testsuite/gdb.arch/powerpc-plxv-nonrel.s
|
|
@@ -0,0 +1,44 @@
|
|
+# Copyright 2021 Free Software Foundation, Inc.
|
|
+
|
|
+# This program is free software; you can redistribute it and/or modify
|
|
+# it under the terms of the GNU General Public License as published by
|
|
+# the Free Software Foundation; either version 3 of the License, or
|
|
+# (at your option) any later version.
|
|
+#
|
|
+# This program is distributed in the hope that it will be useful,
|
|
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+# GNU General Public License for more details.
|
|
+#
|
|
+# You should have received a copy of the GNU General Public License
|
|
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+
|
|
+
|
|
+# test to verify that the prefixed instructions that
|
|
+# load/store non-relative values work OK.
|
|
+
|
|
+.global main
|
|
+.type main,function
|
|
+main:
|
|
+ nop
|
|
+ lnia 4
|
|
+ addi 4,4,40
|
|
+ plxv 4,4(4),0
|
|
+ plxv 5,12(4),0
|
|
+ plxv 6,20(4),0
|
|
+ plxv 7,28(4),0
|
|
+check_here:
|
|
+ blr
|
|
+mydata:
|
|
+ .long 0xa1b1c1d1 # <<-
|
|
+ .long 0xa2b2c2d2 # <<- loaded into vs4
|
|
+ .long 0xa3b3c3d3 # <<- loaded into vs4
|
|
+ .long 0xa4b4c4d4 # <<- loaded into vs4, vs5
|
|
+ .long 0xa5b5c5d5 # <<- loaded into vs4, vs5
|
|
+ .long 0xa6b6c6d6 # <<- loaded into vs5, vs6
|
|
+ .long 0xa7b7c7d7 # <<- loaded into vs5, vs6
|
|
+ .long 0xa8b8c8d8 # <<- loaded into vs6, vs7
|
|
+ .long 0xa9b9c9d9 # <<- loaded into vs6, vs7
|
|
+ .long 0xaabacada # <<- loaded into vs7
|
|
+ .long 0xabbbcbdb # <<- loaded into vs7
|
|
+ .long 0xacbcccdc # <<-
|