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114 lines
5.9 KiB
114 lines
5.9 KiB
2 years ago
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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Andreas Krebbel <krebbel@linux.ibm.com>
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Date: Fri, 4 Dec 2020 09:00:43 +0100
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Subject: gdb-rhbz2012818-ibmz-update-2of5.patch
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;; IBM Z: Add risbgz and risbgnz extended mnemonics
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;; (Andreas Krebbel, RHBZ 2012818)
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These two extended mnemonics are documented in the Principles of
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Operations manual but currently not supported by Binutils. They
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provide aliases for already supported instructions with the zero flag
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being set. The flag otherwise is mingled into one of the immediate
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operands what makes asm code much harder to read.
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opcodes/
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* s390-opc.txt: Add risbgz and risbgnz.
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* s390-opc.c (U6_26): New operand type.
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(INSTR_RIE_RRUUU2, MASK_RIE_RRUUU2): New instruction format and
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mask.
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gas/
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* testsuite/gas/s390/zarch-z10.s: Add tests for risbgz.
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* testsuite/gas/s390/zarch-z10.d: Add regexp for risbgz.
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* testsuite/gas/s390/zarch-zEC12.s: Add tests for risbgnz.
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* testsuite/gas/s390/zarch-zEC12.d: Add regexp for risbgnz.
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diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
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--- a/opcodes/s390-opc.c
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+++ b/opcodes/s390-opc.c
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@@ -218,32 +218,34 @@ const struct s390_operand s390_operands[] =
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{ 8, 8, 0 },
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#define U8_16 68 /* 8 bit unsigned value starting at 16 */
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{ 8, 16, 0 },
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-#define U8_24 69 /* 8 bit unsigned value starting at 24 */
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+#define U6_26 69 /* 6 bit unsigned value starting at 26 */
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+ { 6, 26, 0 },
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+#define U8_24 70 /* 8 bit unsigned value starting at 24 */
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{ 8, 24, 0 },
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-#define U8_28 70 /* 8 bit unsigned value starting at 28 */
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+#define U8_28 71 /* 8 bit unsigned value starting at 28 */
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{ 8, 28, 0 },
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-#define U8_32 71 /* 8 bit unsigned value starting at 32 */
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+#define U8_32 72 /* 8 bit unsigned value starting at 32 */
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{ 8, 32, 0 },
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-#define U12_16 72 /* 12 bit unsigned value starting at 16 */
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+#define U12_16 73 /* 12 bit unsigned value starting at 16 */
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{ 12, 16, 0 },
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-#define U16_16 73 /* 16 bit unsigned value starting at 16 */
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+#define U16_16 74 /* 16 bit unsigned value starting at 16 */
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{ 16, 16, 0 },
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-#define U16_32 74 /* 16 bit unsigned value starting at 32 */
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+#define U16_32 75 /* 16 bit unsigned value starting at 32 */
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{ 16, 32, 0 },
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-#define U32_16 75 /* 32 bit unsigned value starting at 16 */
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+#define U32_16 76 /* 32 bit unsigned value starting at 16 */
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{ 32, 16, 0 },
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/* PC-relative address operands. */
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-#define J12_12 76 /* 12 bit PC relative offset at 12 */
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+#define J12_12 77 /* 12 bit PC relative offset at 12 */
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{ 12, 12, S390_OPERAND_PCREL },
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-#define J16_16 77 /* 16 bit PC relative offset at 16 */
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+#define J16_16 78 /* 16 bit PC relative offset at 16 */
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{ 16, 16, S390_OPERAND_PCREL },
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-#define J16_32 78 /* 16 bit PC relative offset at 32 */
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+#define J16_32 79 /* 16 bit PC relative offset at 32 */
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{ 16, 32, S390_OPERAND_PCREL },
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-#define J24_24 79 /* 24 bit PC relative offset at 24 */
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+#define J24_24 80 /* 24 bit PC relative offset at 24 */
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{ 24, 24, S390_OPERAND_PCREL },
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-#define J32_16 80 /* 32 bit PC relative offset at 16 */
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+#define J32_16 81 /* 32 bit PC relative offset at 16 */
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{ 32, 16, S390_OPERAND_PCREL },
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};
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@@ -313,6 +315,7 @@ const struct s390_operand s390_operands[] =
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#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
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#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
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#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
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+#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
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#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
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#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
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#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
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@@ -534,6 +537,7 @@ const struct s390_operand s390_operands[] =
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#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
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#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
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--- a/opcodes/s390-opc.txt
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+++ b/opcodes/s390-opc.txt
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@@ -970,6 +970,7 @@ ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
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ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
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ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
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ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
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+ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
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c40f strl RIL_RP "store relative long (32)" z10 zarch
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c40b stgrl RIL_RP "store relative long (64)" z10 zarch
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c407 sthrl RIL_RP "store halfword relative long" z10 zarch
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@@ -1153,6 +1154,7 @@ eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zar
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eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
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ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
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+ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
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ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
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ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
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ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
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