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90 lines
3.4 KiB
90 lines
3.4 KiB
2 years ago
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commit 6c175b3d170de2bb02b7bd45b3348eec05d28451
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Author: Roger Sayle <roger@nextmovesoftware.com>
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Date: Mon Jul 4 13:58:37 2022 +0100
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PR target/105991: Recognize PLUS and XOR forms of rldimi in rs6000.md.
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This patch addresses PR target/105991 where a change to prefer representing
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shifts and adds at the tree-level as multiplications, causes problems for
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the rldimi patterns in the powerpc backend. The issue is that rs6000.md
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models this pattern using IOR, and some variants that have the equivalent
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PLUS or XOR in the RTL fail to match some *rotl<mode>4_insert patterns.
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This is fixed in this patch by adding a define_insn_and_split to locally
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canonicalize the PLUS and XOR forms to the backend's preferred IOR form.
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Backported from master.
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2022-07-04 Roger Sayle <roger@nextmovesoftware.com>
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Marek Polacek <polacek@redhat.com>
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Segher Boessenkool <segher@kernel.crashing.org>
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Kewen Lin <linkw@linux.ibm.com>
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gcc/ChangeLog
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PR target/105991
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* config/rs6000/rs6000.md (rotl<mode>3_insert_3): Check that
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exact_log2 doesn't return -1 (or zero).
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(plus_xor): New code iterator.
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(*rotl<mode>3_insert_3_<code>): New define_insn_and_split.
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gcc/testsuite/ChangeLog
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PR target/105991
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* gcc.target/powerpc/pr105991.c: New test case.
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diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
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index 64049a6e521..6082ded8c31 100644
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--- a/gcc/config/rs6000/rs6000.md
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+++ b/gcc/config/rs6000/rs6000.md
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@@ -4178,7 +4178,8 @@ (define_insn "rotl<mode>3_insert_3"
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(match_operand:GPR 4 "const_int_operand" "n"))
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(ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "n"))))]
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- "INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)"
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+ "INTVAL (operands[2]) > 0
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+ && INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)"
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{
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if (<MODE>mode == SImode)
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return "rlwimi %0,%1,%h2,0,31-%h2";
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@@ -4187,6 +4188,24 @@ (define_insn "rotl<mode>3_insert_3"
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}
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[(set_attr "type" "insert")])
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+; Canonicalize the PLUS and XOR forms to IOR for rotl<mode>3_insert_3
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+(define_code_iterator plus_xor [plus xor])
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+
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+(define_insn_and_split "*rotl<mode>3_insert_3_<code>"
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+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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+ (plus_xor:GPR
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+ (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
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+ (match_operand:GPR 4 "const_int_operand" "n"))
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+ (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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+ (match_operand:SI 2 "const_int_operand" "n"))))]
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+ "INTVAL (operands[2]) > 0
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+ && INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)"
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+ "#"
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+ "&& 1"
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+ [(set (match_dup 0)
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+ (ior:GPR (and:GPR (match_dup 3) (match_dup 4))
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+ (ashift:GPR (match_dup 1) (match_dup 2))))])
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+
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(define_code_iterator plus_ior_xor [plus ior xor])
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(define_split
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diff --git a/gcc/testsuite/gcc.target/powerpc/pr105991.c b/gcc/testsuite/gcc.target/powerpc/pr105991.c
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new file mode 100644
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index 00000000000..0d9d130cb63
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/powerpc/pr105991.c
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@@ -0,0 +1,12 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2" } */
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+/* { dg-require-effective-target lp64 } */
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+unsigned long long
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+foo (unsigned long long value)
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+{
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+ value &= 0xffffffff;
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+ value |= value << 32;
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+ return value;
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+}
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+/* { dg-final { scan-assembler {\mrldimi\M} } } */
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+
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