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307 lines
12 KiB
307 lines
12 KiB
2 months ago
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commit ca6eea0eb33de8b2e23e0bef3466575bb14ab63f
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Author: Kewen Lin <linkw@linux.ibm.com>
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Date: Wed Jun 26 02:16:17 2024 -0500
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rs6000: Fix wrong RTL patterns for vector merge high/low short on LE
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Commit r12-4496 changes some define_expands and define_insns
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for vector merge high/low short, which are altivec_vmrg[hl]h.
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These defines are mainly for built-in function vec_merge{h,l}
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and some internal gen function needs. These functions should
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consider endianness, taking vec_mergeh as example, as PVIPR
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defines, vec_mergeh "Merges the first halves (in element order)
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of two vectors", it does note it's in element order. So it's
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mapped into vmrghh on BE while vmrglh on LE respectively.
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Although the mapped insns are different, as the discussion in
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PR106069, the RTL pattern should be still the same, it is
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conformed before commit r12-4496, but gets changed into
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different patterns on BE and LE starting from commit r12-4496.
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Similar to 32-bit element case in commit log of r15-1504, this
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16-bit element pattern on LE doesn't actually match what the
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underlying insn is intended to represent, once some optimization
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like combine does some changes basing on it, it would cause
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the unexpected consequence. The newly constructed test case
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pr106069-2.c is a typical example for this issue on element type
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short.
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So this patch is to fix the wrong RTL pattern, ensure the
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associated RTL patterns become the same as before which can
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have the same semantic as their mapped insns. With the
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proposed patch, the expanders like altivec_vmrghh expands
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into altivec_vmrghh_direct_be or altivec_vmrglh_direct_le
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depending on endianness, "direct" can easily show which
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insn would be generated, _be and _le are mainly for the
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different RTL patterns as endianness.
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Co-authored-by: Xionghu Luo <xionghuluo@tencent.com>
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PR target/106069
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PR target/115355
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gcc/ChangeLog:
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* config/rs6000/altivec.md (altivec_vmrghh_direct): Rename to ...
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(altivec_vmrghh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.
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(altivec_vmrghh_direct_le): New define_insn.
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(altivec_vmrglh_direct): Rename to ...
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(altivec_vmrglh_direct_be): ... this. Add condition BYTES_BIG_ENDIAN.
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(altivec_vmrglh_direct_le): New define_insn.
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(altivec_vmrghh): Adjust by calling gen_altivec_vmrghh_direct_be
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for BE and gen_altivec_vmrglh_direct_le for LE.
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(altivec_vmrglh): Adjust by calling gen_altivec_vmrglh_direct_be
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for BE and gen_altivec_vmrghh_direct_le for LE.
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(vec_widen_umult_hi_v16qi): Adjust the call to
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gen_altivec_vmrghh_direct by gen_altivec_vmrghh for BE
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and by gen_altivec_vmrglh for LE.
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(vec_widen_smult_hi_v16qi): Likewise.
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(vec_widen_umult_lo_v16qi): Adjust the call to
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gen_altivec_vmrglh_direct by gen_altivec_vmrglh for BE
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and by gen_altivec_vmrghh for LE.
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(vec_widen_smult_lo_v16qi): Likewise.
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* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Replace
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CODE_FOR_altivec_vmrghh_direct by
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CODE_FOR_altivec_vmrghh_direct_be for BE and
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CODE_FOR_altivec_vmrghh_direct_le for LE. And replace
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CODE_FOR_altivec_vmrglh_direct by
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CODE_FOR_altivec_vmrglh_direct_be for BE and
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CODE_FOR_altivec_vmrglh_direct_le for LE.
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gcc/testsuite/ChangeLog:
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* gcc.target/powerpc/pr106069-2.c: New test.
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(cherry picked from commit 812c70bf4981958488331d4ea5af8709b5321da1)
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diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
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index b8baae679c4..50689e418ed 100644
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--- a/gcc/config/rs6000/altivec.md
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+++ b/gcc/config/rs6000/altivec.md
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@@ -1203,17 +1203,18 @@ (define_expand "altivec_vmrghh"
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(use (match_operand:V8HI 2 "register_operand"))]
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"TARGET_ALTIVEC"
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{
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- rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrghh_direct
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- : gen_altivec_vmrglh_direct;
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- if (!BYTES_BIG_ENDIAN)
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- std::swap (operands[1], operands[2]);
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- emit_insn (fun (operands[0], operands[1], operands[2]));
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+ if (BYTES_BIG_ENDIAN)
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+ emit_insn (
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+ gen_altivec_vmrghh_direct_be (operands[0], operands[1], operands[2]));
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+ else
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+ emit_insn (
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+ gen_altivec_vmrglh_direct_le (operands[0], operands[2], operands[1]));
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DONE;
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})
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-(define_insn "altivec_vmrghh_direct"
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+(define_insn "altivec_vmrghh_direct_be"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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- (vec_select:V8HI
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+ (vec_select:V8HI
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(vec_concat:V16HI
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(match_operand:V8HI 1 "register_operand" "v")
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(match_operand:V8HI 2 "register_operand" "v"))
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@@ -1221,7 +1222,21 @@ (define_insn "altivec_vmrghh_direct"
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(const_int 1) (const_int 9)
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(const_int 2) (const_int 10)
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(const_int 3) (const_int 11)])))]
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- "TARGET_ALTIVEC"
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+ "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
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+ "vmrghh %0,%1,%2"
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+ [(set_attr "type" "vecperm")])
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+
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+(define_insn "altivec_vmrghh_direct_le"
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+ [(set (match_operand:V8HI 0 "register_operand" "=v")
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+ (vec_select:V8HI
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+ (vec_concat:V16HI
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+ (match_operand:V8HI 2 "register_operand" "v")
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+ (match_operand:V8HI 1 "register_operand" "v"))
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+ (parallel [(const_int 4) (const_int 12)
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+ (const_int 5) (const_int 13)
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+ (const_int 6) (const_int 14)
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+ (const_int 7) (const_int 15)])))]
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+ "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
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"vmrghh %0,%1,%2"
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[(set_attr "type" "vecperm")])
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@@ -1344,15 +1359,16 @@ (define_expand "altivec_vmrglh"
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(use (match_operand:V8HI 2 "register_operand"))]
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"TARGET_ALTIVEC"
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{
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- rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrglh_direct
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- : gen_altivec_vmrghh_direct;
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- if (!BYTES_BIG_ENDIAN)
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- std::swap (operands[1], operands[2]);
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- emit_insn (fun (operands[0], operands[1], operands[2]));
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+ if (BYTES_BIG_ENDIAN)
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+ emit_insn (
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+ gen_altivec_vmrglh_direct_be (operands[0], operands[1], operands[2]));
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+ else
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+ emit_insn (
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+ gen_altivec_vmrghh_direct_le (operands[0], operands[2], operands[1]));
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DONE;
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})
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-(define_insn "altivec_vmrglh_direct"
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+(define_insn "altivec_vmrglh_direct_be"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(vec_select:V8HI
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(vec_concat:V16HI
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@@ -1362,7 +1378,21 @@ (define_insn "altivec_vmrglh_direct"
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(const_int 5) (const_int 13)
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(const_int 6) (const_int 14)
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(const_int 7) (const_int 15)])))]
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- "TARGET_ALTIVEC"
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+ "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
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+ "vmrglh %0,%1,%2"
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+ [(set_attr "type" "vecperm")])
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+
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+(define_insn "altivec_vmrglh_direct_le"
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+ [(set (match_operand:V8HI 0 "register_operand" "=v")
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+ (vec_select:V8HI
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+ (vec_concat:V16HI
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+ (match_operand:V8HI 2 "register_operand" "v")
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+ (match_operand:V8HI 1 "register_operand" "v"))
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+ (parallel [(const_int 0) (const_int 8)
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+ (const_int 1) (const_int 9)
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+ (const_int 2) (const_int 10)
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+ (const_int 3) (const_int 11)])))]
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+ "TARGET_ALTIVEC && !BYTES_BIG_ENDIAN"
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"vmrglh %0,%1,%2"
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[(set_attr "type" "vecperm")])
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@@ -3777,13 +3807,13 @@ (define_expand "vec_widen_umult_hi_v16qi"
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{
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emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
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+ emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
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}
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else
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{
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emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
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+ emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
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}
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DONE;
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})
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@@ -3802,13 +3832,13 @@ (define_expand "vec_widen_umult_lo_v16qi"
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{
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emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
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+ emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
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}
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else
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{
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emit_insn (gen_altivec_vmuloub (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmuleub (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
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+ emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
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}
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DONE;
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})
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@@ -3827,13 +3857,13 @@ (define_expand "vec_widen_smult_hi_v16qi"
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{
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emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrghh_direct (operands[0], ve, vo));
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+ emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
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}
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else
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{
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emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
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+ emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
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}
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DONE;
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})
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@@ -3852,13 +3882,13 @@ (define_expand "vec_widen_smult_lo_v16qi"
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{
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emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrglh_direct (operands[0], ve, vo));
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+ emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
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}
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else
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{
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emit_insn (gen_altivec_vmulosb (ve, operands[1], operands[2]));
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emit_insn (gen_altivec_vmulesb (vo, operands[1], operands[2]));
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- emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
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+ emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
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}
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DONE;
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})
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diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
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index e8ce629182b..34be43c9f84 100644
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--- a/gcc/config/rs6000/rs6000.cc
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+++ b/gcc/config/rs6000/rs6000.cc
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@@ -22975,8 +22975,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
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: CODE_FOR_altivec_vmrglb_direct_le,
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{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}},
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{OPTION_MASK_ALTIVEC,
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- BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
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- : CODE_FOR_altivec_vmrglh_direct,
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+ BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct_be
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+ : CODE_FOR_altivec_vmrglh_direct_le,
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{0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}},
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{OPTION_MASK_ALTIVEC,
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BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct_v4si_be
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@@ -22987,8 +22987,8 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
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: CODE_FOR_altivec_vmrghb_direct_le,
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{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}},
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{OPTION_MASK_ALTIVEC,
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- BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
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- : CODE_FOR_altivec_vmrghh_direct,
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+ BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct_be
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+ : CODE_FOR_altivec_vmrghh_direct_le,
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{8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}},
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{OPTION_MASK_ALTIVEC,
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BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct_v4si_be
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diff --git a/gcc/testsuite/gcc.target/powerpc/pr106069-2.c b/gcc/testsuite/gcc.target/powerpc/pr106069-2.c
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new file mode 100644
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index 00000000000..283e3290fb3
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/powerpc/pr106069-2.c
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@@ -0,0 +1,37 @@
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+/* { dg-do run } */
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+/* { dg-options "-O2" } */
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+/* { dg-require-effective-target vmx_hw } */
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+
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+/* Test vector merge for 16-bit element size,
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+ it will abort if the RTL pattern isn't expected. */
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+
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+#include "altivec.h"
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+
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+__attribute__((noipa))
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||
|
|
+signed short elem_2 (vector signed short a, vector signed short b)
|
||
|
|
+{
|
||
|
|
+ vector signed short c = vec_mergeh (a,b);
|
||
|
|
+ return vec_extract (c, 2);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+__attribute__((noipa))
|
||
|
|
+unsigned short elem_7 (vector unsigned short a, vector unsigned short b)
|
||
|
|
+{
|
||
|
|
+ vector unsigned short c = vec_mergel (a,b);
|
||
|
|
+ return vec_extract (c, 7);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+main ()
|
||
|
|
+{
|
||
|
|
+ vector unsigned short v1 = {3, 22, 12, 34, 5, 25, 30, 11};
|
||
|
|
+ vector unsigned short v2 = {84, 168, 267, 966, 65, 399, 999, 99};
|
||
|
|
+ signed short x1 = elem_2 ((vector signed short) v1, (vector signed short) v2);
|
||
|
|
+ unsigned short x2 = elem_7 (v1, v2);
|
||
|
|
+
|
||
|
|
+ if (x1 != 22 || x2 != 99)
|
||
|
|
+ __builtin_abort ();
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|