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197 lines
8.1 KiB
197 lines
8.1 KiB
3 years ago
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From 80c2ed8228817fb6438120997227811a746272ba Mon Sep 17 00:00:00 2001
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From: "H.J. Lu" <hjl.tools@gmail.com>
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Date: Wed, 15 Sep 2021 14:17:08 +0800
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Subject: [PATCH 2/3] x86: Update memcpy/memset inline strategies for
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-mtune=tremont
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Simply memcpy and memset inline strategies to avoid branches for
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-mtune=tremont:
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1. Create Tremont cost model from generic cost model.
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2. With MOVE_RATIO and CLEAR_RATIO == 17, GCC will use integer/vector
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load and store for up to 16 * 16 (256) bytes when the data size is
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fixed and known.
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3. Inline only if data size is known to be <= 256.
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a. Use "rep movsb/stosb" with simple code sequence if the data size
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is a constant.
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b. Use loop if data size is not a constant.
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4. Use memcpy/memset libray function if data size is unknown or > 256.
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* config/i386/i386-options.c (processor_cost_table): Use
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tremont_cost for Tremont.
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* config/i386/x86-tune-costs.h (tremont_memcpy): New.
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(tremont_memset): Likewise.
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(tremont_cost): Likewise.
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* config/i386/x86-tune.def (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB):
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Enable for Tremont.
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---
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gcc/config/i386/i386-options.c | 2 +-
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gcc/config/i386/x86-tune-costs.h | 124 +++++++++++++++++++++++++++++++
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gcc/config/i386/x86-tune.def | 2 +-
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3 files changed, 126 insertions(+), 2 deletions(-)
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diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
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index 19632b5fd6b..4b77d62926f 100644
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--- a/gcc/config/i386/i386-options.c
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+++ b/gcc/config/i386/i386-options.c
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@@ -719,7 +719,7 @@ static const struct processor_costs *processor_cost_table[] =
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&slm_cost,
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&slm_cost,
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&slm_cost,
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- &slm_cost,
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+ &tremont_cost,
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&slm_cost,
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&slm_cost,
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&skylake_cost,
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diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
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index ffe810f2bcb..93644be9cb3 100644
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--- a/gcc/config/i386/x86-tune-costs.h
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+++ b/gcc/config/i386/x86-tune-costs.h
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@@ -2734,6 +2734,130 @@ struct processor_costs slm_cost = {
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"16", /* Func alignment. */
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};
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+static stringop_algs tremont_memcpy[2] = {
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+ {libcall,
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+ {{256, rep_prefix_1_byte, true},
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+ {256, loop, false},
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+ {-1, libcall, false}}},
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+ {libcall,
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+ {{256, rep_prefix_1_byte, true},
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+ {256, loop, false},
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+ {-1, libcall, false}}}};
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+static stringop_algs tremont_memset[2] = {
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+ {libcall,
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+ {{256, rep_prefix_1_byte, true},
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+ {256, loop, false},
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+ {-1, libcall, false}}},
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+ {libcall,
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+ {{256, rep_prefix_1_byte, true},
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+ {256, loop, false},
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+ {-1, libcall, false}}}};
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+static const
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+struct processor_costs tremont_cost = {
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+ {
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+ /* Start of register allocator costs. integer->integer move cost is 2. */
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+ 6, /* cost for loading QImode using movzbl */
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+ {6, 6, 6}, /* cost of loading integer registers
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+ in QImode, HImode and SImode.
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+ Relative to reg-reg move (2). */
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+ {6, 6, 6}, /* cost of storing integer registers */
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+ 4, /* cost of reg,reg fld/fst */
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+ {6, 6, 12}, /* cost of loading fp registers
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+ in SFmode, DFmode and XFmode */
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+ {6, 6, 12}, /* cost of storing fp registers
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+ in SFmode, DFmode and XFmode */
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+ 2, /* cost of moving MMX register */
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+ {6, 6}, /* cost of loading MMX registers
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+ in SImode and DImode */
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+ {6, 6}, /* cost of storing MMX registers
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+ in SImode and DImode */
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+ 2, 3, 4, /* cost of moving XMM,YMM,ZMM register */
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+ {6, 6, 6, 10, 15}, /* cost of loading SSE registers
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+ in 32,64,128,256 and 512-bit */
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+ {6, 6, 6, 10, 15}, /* cost of storing SSE registers
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+ in 32,64,128,256 and 512-bit */
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+ 6, 6, /* SSE->integer and integer->SSE moves */
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+ 6, 6, /* mask->integer and integer->mask moves */
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+ {6, 6, 6}, /* cost of loading mask register
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+ in QImode, HImode, SImode. */
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+ {6, 6, 6}, /* cost if storing mask register
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+ in QImode, HImode, SImode. */
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+ 2, /* cost of moving mask register. */
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+ /* End of register allocator costs. */
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+ },
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+
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+ COSTS_N_INSNS (1), /* cost of an add instruction */
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+ /* Setting cost to 2 makes our current implementation of synth_mult result in
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+ use of unnecessary temporary registers causing regression on several
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+ SPECfp benchmarks. */
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+ COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
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+ COSTS_N_INSNS (1), /* variable shift costs */
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+ COSTS_N_INSNS (1), /* constant shift costs */
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+ {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
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+ COSTS_N_INSNS (4), /* HI */
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+ COSTS_N_INSNS (3), /* SI */
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+ COSTS_N_INSNS (4), /* DI */
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+ COSTS_N_INSNS (4)}, /* other */
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+ 0, /* cost of multiply per each bit set */
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+ {COSTS_N_INSNS (16), /* cost of a divide/mod for QI */
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+ COSTS_N_INSNS (22), /* HI */
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+ COSTS_N_INSNS (30), /* SI */
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+ COSTS_N_INSNS (74), /* DI */
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+ COSTS_N_INSNS (74)}, /* other */
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+ COSTS_N_INSNS (1), /* cost of movsx */
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+ COSTS_N_INSNS (1), /* cost of movzx */
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+ 8, /* "large" insn */
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+ 17, /* MOVE_RATIO */
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+ 17, /* CLEAR_RATIO */
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+ {6, 6, 6}, /* cost of loading integer registers
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+ in QImode, HImode and SImode.
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+ Relative to reg-reg move (2). */
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+ {6, 6, 6}, /* cost of storing integer registers */
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+ {6, 6, 6, 10, 15}, /* cost of loading SSE register
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+ in 32bit, 64bit, 128bit, 256bit and 512bit */
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+ {6, 6, 6, 10, 15}, /* cost of storing SSE register
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+ in 32bit, 64bit, 128bit, 256bit and 512bit */
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+ {6, 6, 6, 10, 15}, /* cost of unaligned loads. */
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+ {6, 6, 6, 10, 15}, /* cost of unaligned storess. */
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+ 2, 3, 4, /* cost of moving XMM,YMM,ZMM register */
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+ 6, /* cost of moving SSE register to integer. */
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+ 18, 6, /* Gather load static, per_elt. */
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+ 18, 6, /* Gather store static, per_elt. */
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+ 32, /* size of l1 cache. */
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+ 512, /* size of l2 cache. */
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+ 64, /* size of prefetch block */
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+ 6, /* number of parallel prefetches */
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+ /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
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+ value is increased to perhaps more appropriate value of 5. */
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+ 3, /* Branch cost */
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+ COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
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+ COSTS_N_INSNS (5), /* cost of FMUL instruction. */
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+ COSTS_N_INSNS (17), /* cost of FDIV instruction. */
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+ COSTS_N_INSNS (1), /* cost of FABS instruction. */
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+ COSTS_N_INSNS (1), /* cost of FCHS instruction. */
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+ COSTS_N_INSNS (14), /* cost of FSQRT instruction. */
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+
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+ COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
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+ COSTS_N_INSNS (3), /* cost of ADDSS/SD SUBSS/SD insns. */
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+ COSTS_N_INSNS (4), /* cost of MULSS instruction. */
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+ COSTS_N_INSNS (5), /* cost of MULSD instruction. */
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+ COSTS_N_INSNS (5), /* cost of FMA SS instruction. */
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+ COSTS_N_INSNS (5), /* cost of FMA SD instruction. */
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+ COSTS_N_INSNS (13), /* cost of DIVSS instruction. */
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+ COSTS_N_INSNS (17), /* cost of DIVSD instruction. */
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+ COSTS_N_INSNS (14), /* cost of SQRTSS instruction. */
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+ COSTS_N_INSNS (18), /* cost of SQRTSD instruction. */
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+ 1, 4, 3, 3, /* reassoc int, fp, vec_int, vec_fp. */
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+ tremont_memcpy,
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+ tremont_memset,
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+ COSTS_N_INSNS (4), /* cond_taken_branch_cost. */
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+ COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
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+ "16:11:8", /* Loop alignment. */
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+ "16:11:8", /* Jump alignment. */
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+ "0:0:8", /* Label alignment. */
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+ "16", /* Func alignment. */
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+};
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+
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static stringop_algs intel_memcpy[2] = {
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{libcall, {{11, loop, false}, {-1, rep_prefix_4_byte, false}}},
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{libcall, {{32, loop, false}, {64, rep_prefix_4_byte, false},
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diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
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index 6bd7087a03f..636e0c788bf 100644
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--- a/gcc/config/i386/x86-tune.def
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+++ b/gcc/config/i386/x86-tune.def
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@@ -273,7 +273,7 @@ DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
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move/set sequences of bytes with known size. */
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DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
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"prefer_known_rep_movsb_stosb",
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- m_SKYLAKE | m_ALDERLAKE | m_CORE_AVX512)
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+ m_SKYLAKE | m_ALDERLAKE | m_TREMONT | m_CORE_AVX512)
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/* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
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compact prologues and epilogues by issuing a misaligned moves. This
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--
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2.18.2
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