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186 lines
7.1 KiB
186 lines
7.1 KiB
3 years ago
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From c4c7244349999f91ef2a7cd2108eee0372490be9 Mon Sep 17 00:00:00 2001
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From: "H.J. Lu" <hjl.tools@gmail.com>
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Date: Wed, 15 Sep 2021 14:18:21 +0800
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Subject: [PATCH 3/3] x86: Add TARGET_SSE_PARTIAL_REG_[FP_]CONVERTS_DEPENDENCY
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1. Replace TARGET_SSE_PARTIAL_REG_DEPENDENCY with
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TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY in SSE FP to FP splitters.
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2. Replace TARGET_SSE_PARTIAL_REG_DEPENDENCY with
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TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY in SSE INT to FP splitters.
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gcc/
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* config/i386/i386.h (TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY):
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New.
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(TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Likewise.
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* config/i386/i386.md (SSE FP to FP splitters): Replace
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TARGET_SSE_PARTIAL_REG_DEPENDENCY with
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TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY.
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(SSE INT to FP splitter): Replace TARGET_SSE_PARTIAL_REG_DEPENDENCY
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with TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY.
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* config/i386/x86-tune.def
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(X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): New.
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(X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Likewise.
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gcc/testsuite/
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* gcc.target/i386/sse-covert-1.c: Likewise.
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* gcc.target/i386/sse-fp-covert-1.c: Likewise.
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* gcc.target/i386/sse-int-covert-1.c: Likewise.
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---
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gcc/config/i386/i386.h | 4 ++++
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gcc/config/i386/i386.md | 9 ++++++---
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gcc/config/i386/x86-tune.def | 15 +++++++++++++++
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gcc/testsuite/gcc.target/i386/sse-covert-1.c | 19 +++++++++++++++++++
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.../gcc.target/i386/sse-fp-covert-1.c | 15 +++++++++++++++
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.../gcc.target/i386/sse-int-covert-1.c | 14 ++++++++++++++
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6 files changed, 73 insertions(+), 3 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/i386/sse-covert-1.c
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create mode 100644 gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c
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create mode 100644 gcc/testsuite/gcc.target/i386/sse-int-covert-1.c
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diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
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index 73e118900f7..5b992195df7 100644
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--- a/gcc/config/i386/i386.h
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+++ b/gcc/config/i386/i386.h
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@@ -553,6 +553,10 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
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ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
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#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
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ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
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+#define TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY \
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+ ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY]
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+#define TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY \
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+ ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY]
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#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
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ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
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#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
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diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
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index 97325e38676..053bec1c1e1 100644
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--- a/gcc/config/i386/i386.md
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+++ b/gcc/config/i386/i386.md
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@@ -4378,7 +4378,8 @@
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(float_extend:DF
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(match_operand:SF 1 "nonimmediate_operand")))]
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"!TARGET_AVX
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- && TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
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+ && TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY
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+ && epilogue_completed
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&& optimize_function_for_speed_p (cfun)
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&& (!REG_P (operands[1])
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|| (!TARGET_AVX && REGNO (operands[0]) != REGNO (operands[1])))
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@@ -4540,7 +4541,8 @@
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(float_truncate:SF
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(match_operand:DF 1 "nonimmediate_operand")))]
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"!TARGET_AVX
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- && TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
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+ && TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY
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+ && epilogue_completed
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&& optimize_function_for_speed_p (cfun)
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&& (!REG_P (operands[1])
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|| (!TARGET_AVX && REGNO (operands[0]) != REGNO (operands[1])))
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@@ -5053,7 +5055,8 @@
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[(set (match_operand:MODEF 0 "sse_reg_operand")
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(float:MODEF (match_operand:SWI48 1 "nonimmediate_operand")))]
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"!TARGET_AVX
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- && TARGET_SSE_PARTIAL_REG_DEPENDENCY && epilogue_completed
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+ && TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY
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+ && epilogue_completed
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&& optimize_function_for_speed_p (cfun)
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&& (!EXT_REX_SSE_REG_P (operands[0])
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|| TARGET_AVX512VL)"
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diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
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index 636e0c788bf..b5166fb1316 100644
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--- a/gcc/config/i386/x86-tune.def
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+++ b/gcc/config/i386/x86-tune.def
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@@ -64,6 +64,21 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
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| m_BDVER | m_ZNVER | m_TREMONT | m_GENERIC)
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+/* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
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+ partial write to the destination in scalar SSE conversion from FP
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+ to FP. */
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+DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
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+ "sse_partial_reg_fp_converts_dependency",
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+ m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
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+ | m_BDVER | m_ZNVER | m_GENERIC)
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+
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+/* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
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+ write to the destination in scalar SSE conversion from integer to FP. */
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+DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
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+ "sse_partial_reg_converts_dependency",
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+ m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
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+ | m_BDVER | m_ZNVER | m_GENERIC)
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+
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/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
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are resolved on SSE register parts instead of whole registers, so we may
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maintain just lower part of scalar values in proper format leaving the
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diff --git a/gcc/testsuite/gcc.target/i386/sse-covert-1.c b/gcc/testsuite/gcc.target/i386/sse-covert-1.c
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new file mode 100644
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index 00000000000..c30af694505
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/i386/sse-covert-1.c
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@@ -0,0 +1,19 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=x86-64 -mfpmath=sse -mtune-ctrl=^sse_partial_reg_fp_converts_dependency,^sse_partial_reg_converts_dependency" } */
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+
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+extern float f;
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+extern double d;
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+extern int i;
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+
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+void
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+foo (void)
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+{
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+ d = f;
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+ f = i;
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+}
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+
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+/* { dg-final { scan-assembler "cvtss2sd" } } */
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+/* { dg-final { scan-assembler "cvtsi2ssl" } } */
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+/* { dg-final { scan-assembler-not "cvtps2pd" } } */
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+/* { dg-final { scan-assembler-not "cvtdq2ps" } } */
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+/* { dg-final { scan-assembler-not "pxor" } } */
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diff --git a/gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c b/gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c
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new file mode 100644
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index 00000000000..b6567e60e3e
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/i386/sse-fp-covert-1.c
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@@ -0,0 +1,15 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=x86-64 -mfpmath=sse -mtune-ctrl=^sse_partial_reg_fp_converts_dependency" } */
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+
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+extern float f;
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+extern double d;
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+
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+void
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+foo (void)
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+{
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+ d = f;
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+}
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+
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+/* { dg-final { scan-assembler "cvtss2sd" } } */
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+/* { dg-final { scan-assembler-not "cvtps2pd" } } */
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+/* { dg-final { scan-assembler-not "pxor" } } */
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diff --git a/gcc/testsuite/gcc.target/i386/sse-int-covert-1.c b/gcc/testsuite/gcc.target/i386/sse-int-covert-1.c
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new file mode 100644
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index 00000000000..107f7241def
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/i386/sse-int-covert-1.c
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@@ -0,0 +1,14 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -march=x86-64 -mfpmath=sse -mtune-ctrl=^sse_partial_reg_converts_dependency" } */
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+
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+extern float f;
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+extern int i;
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+
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+void
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+foo (void)
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+{
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+ f = i;
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+}
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+
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+/* { dg-final { scan-assembler "cvtsi2ssl" } } */
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+/* { dg-final { scan-assembler-not "pxor" } } */
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--
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2.18.2
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