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295 lines
13 KiB
295 lines
13 KiB
3 years ago
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From cbd145b132c79c36e990a0eaf10c86159009f18d Mon Sep 17 00:00:00 2001
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From: "H.J. Lu" <hjl.tools@gmail.com>
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Date: Wed, 15 Sep 2021 14:15:10 +0800
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Subject: [PATCH 1/3] x86: Update -mtune=tremont
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Initial -mtune=tremont update
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1. Use Haswell scheduling model.
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2. Assume that stack engine allows to execute push&pop instructions in
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parall.
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3. Prepare for scheduling pass as -mtune=generic.
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4. Use the same issue rate as -mtune=generic.
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5. Enable partial_reg_dependency.
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6. Disable accumulate_outgoing_args
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7. Enable use_leave
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8. Enable push_memory
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9. Disable four_jump_limit
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10. Disable opt_agu
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11. Disable avoid_lea_for_addr
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12. Disable avoid_mem_opnd_for_cmove
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13. Enable misaligned_move_string_pro_epilogues
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14. Enable use_cltd
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16. Enable avoid_false_dep_for_bmi
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17. Enable avoid_mfence
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18. Disable expand_abs
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19. Enable sse_typeless_stores
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20. Enable sse_load0_by_pxor
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21. Disable split_mem_opnd_for_fp_converts
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22. Disable slow_pshufb
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23. Enable partial_reg_dependency
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This is the first patch to tune for Tremont. With all patches applied,
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performance impacts on SPEC CPU 2017 are:
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500.perlbench_r 1.81%
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502.gcc_r 0.57%
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505.mcf_r 1.16%
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520.omnetpp_r 0.00%
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523.xalancbmk_r 0.00%
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525.x264_r 4.55%
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531.deepsjeng_r 0.00%
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541.leela_r 0.39%
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548.exchange2_r 1.13%
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557.xz_r 0.00%
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geomean for intrate 0.95%
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503.bwaves_r 0.00%
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507.cactuBSSN_r 6.94%
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508.namd_r 12.37%
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510.parest_r 1.01%
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511.povray_r 3.70%
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519.lbm_r 36.61%
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521.wrf_r 8.79%
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526.blender_r 2.91%
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527.cam4_r 6.23%
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538.imagick_r 0.28%
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544.nab_r 21.99%
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549.fotonik3d_r 3.63%
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554.roms_r -1.20%
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geomean for fprate 7.50%
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gcc/ChangeLog
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* common/config/i386/i386-common.c: Use Haswell scheduling model
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for Tremont.
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* config/i386/i386.c (ix86_sched_init_global): Prepare for Tremont
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scheduling pass.
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* config/i386/x86-tune-sched.c (ix86_issue_rate): Change Tremont
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issue rate to 4.
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(ix86_adjust_cost): Handle Tremont.
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* config/i386/x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY):
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Enable for Tremont.
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(X86_TUNE_USE_LEAVE): Likewise.
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(X86_TUNE_PUSH_MEMORY): Likewise.
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(X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Likewise.
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(X86_TUNE_USE_CLTD): Likewise.
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(X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Likewise.
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(X86_TUNE_AVOID_MFENCE): Likewise.
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(X86_TUNE_SSE_TYPELESS_STORES): Likewise.
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(X86_TUNE_SSE_LOAD0_BY_PXOR): Likewise.
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(X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Disable for Tremont.
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(X86_TUNE_FOUR_JUMP_LIMIT): Likewise.
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(X86_TUNE_OPT_AGU): Likewise.
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(X86_TUNE_AVOID_LEA_FOR_ADDR): Likewise.
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(X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE): Likewise.
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(X86_TUNE_EXPAND_ABS): Likewise.
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(X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS): Likewise.
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(X86_TUNE_SLOW_PSHUFB): Likewise.
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---
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gcc/common/config/i386/i386-common.c | 2 +-
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gcc/config/i386/i386.c | 1 +
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gcc/config/i386/x86-tune-sched.c | 2 ++
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gcc/config/i386/x86-tune.def | 37 ++++++++++++++--------------
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4 files changed, 23 insertions(+), 19 deletions(-)
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diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
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index 38dbb9d9263..ef382ec9a22 100644
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--- a/gcc/common/config/i386/i386-common.c
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+++ b/gcc/common/config/i386/i386-common.c
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@@ -1916,7 +1916,7 @@ const pta processor_alias_table[] =
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M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
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{"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
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M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
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- {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT,
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+ {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
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M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
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{"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL,
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M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F},
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diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
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index 42c47d2b12b..fc2a27b5cbf 100644
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--- a/gcc/config/i386/i386.c
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+++ b/gcc/config/i386/i386.c
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@@ -16732,6 +16732,7 @@ ix86_sched_init_global (FILE *, int, int)
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case PROCESSOR_NEHALEM:
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case PROCESSOR_SANDYBRIDGE:
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case PROCESSOR_HASWELL:
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+ case PROCESSOR_TREMONT:
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case PROCESSOR_GENERIC:
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/* Do not perform multipass scheduling for pre-reload schedule
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to save compile time. */
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diff --git a/gcc/config/i386/x86-tune-sched.c b/gcc/config/i386/x86-tune-sched.c
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index 2bcc64b865a..278035eec0b 100644
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--- a/gcc/config/i386/x86-tune-sched.c
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+++ b/gcc/config/i386/x86-tune-sched.c
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@@ -71,6 +71,7 @@ ix86_issue_rate (void)
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case PROCESSOR_NEHALEM:
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case PROCESSOR_SANDYBRIDGE:
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case PROCESSOR_HASWELL:
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+ case PROCESSOR_TREMONT:
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case PROCESSOR_GENERIC:
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return 4;
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@@ -430,6 +431,7 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
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case PROCESSOR_NEHALEM:
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case PROCESSOR_SANDYBRIDGE:
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case PROCESSOR_HASWELL:
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+ case PROCESSOR_TREMONT:
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case PROCESSOR_GENERIC:
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/* Stack engine allows to execute push&pop instructions in parall. */
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if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
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diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
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index eb057a67750..6bd7087a03f 100644
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--- a/gcc/config/i386/x86-tune.def
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+++ b/gcc/config/i386/x86-tune.def
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@@ -62,7 +62,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
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that can be partly masked by careful scheduling of moves. */
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DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
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- | m_BDVER | m_ZNVER | m_GENERIC)
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+ | m_BDVER | m_ZNVER | m_TREMONT | m_GENERIC)
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/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
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are resolved on SSE register parts instead of whole registers, so we may
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@@ -136,7 +136,7 @@ DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
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DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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- | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ATHLON_K8)
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+ | m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
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considered on critical path. */
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@@ -150,14 +150,15 @@ DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
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/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
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DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
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- m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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+ m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_TREMONT
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+ | m_GENERIC)
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/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
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Some chips, like 486 and Pentium works faster with separate load
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and push instructions. */
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DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
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m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
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- | m_GENERIC)
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+ | m_TREMONT | m_GENERIC)
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/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
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over esp subtraction. */
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@@ -198,8 +199,7 @@ DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
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than 4 branch instructions in the 16 byte window. */
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DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
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- | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL | m_ATHLON_K8
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- | m_AMDFAM10)
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+ | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
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/*****************************************************************************/
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/* Integer instruction selection tuning */
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@@ -240,11 +240,11 @@ DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
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/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
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will impact LEA instruction selection. */
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DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
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- | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
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+ | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
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/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
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DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
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- m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
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+ m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS
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| m_KNL | m_KNM)
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/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
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@@ -263,7 +263,7 @@ DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
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a conditional move. */
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DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
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m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
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- | m_KNM | m_TREMONT | m_INTEL)
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+ | m_KNM | m_INTEL)
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/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
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as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
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@@ -282,7 +282,8 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
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FIXME: This may actualy be a win on more targets than listed here. */
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DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
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"misaligned_move_string_pro_epilogues",
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- m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC)
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+ m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_TREMONT
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+ | m_GENERIC)
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/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
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DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
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@@ -294,7 +295,7 @@ DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
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/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
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DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
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~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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- | m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT))
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+ | m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS))
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/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
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DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
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@@ -305,7 +306,7 @@ DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
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/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
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for bit-manipulation instructions. */
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DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
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- m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC)
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+ m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_GENERIC)
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/* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
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on hardware capabilities. Bdver3 hardware has a loop buffer which makes
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@@ -321,14 +322,14 @@ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
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/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
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DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
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- m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
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+ m_CORE_ALL | m_BDVER | m_ZNVER | m_TREMONT | m_GENERIC)
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/* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
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generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
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(signed) x >> (W-1)) instead of cmove or SSE max/abs instructions. */
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DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs",
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m_CORE_ALL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
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- | m_GOLDMONT_PLUS | m_TREMONT )
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+ | m_GOLDMONT_PLUS)
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/*****************************************************************************/
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/* 387 instruction selection tuning */
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@@ -386,13 +387,13 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim
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/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
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DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
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- m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC)
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+ m_AMD_MULTIPLE | m_CORE_ALL | m_TREMONT | m_GENERIC)
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/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
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xorps/xorpd and other variants. */
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DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
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- | m_GENERIC)
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+ | m_TREMONT | m_GENERIC)
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/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
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to SSE registers. If disabled, the moves will be done by storing
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@@ -419,7 +420,7 @@ DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
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fp converts to destination register. */
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DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
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m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS
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- | m_TREMONT | m_INTEL)
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+ | m_INTEL)
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||
|
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||
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/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
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||
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|
from FP to FP. This form of instructions avoids partial write to the
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||
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@@ -434,7 +435,7 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
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/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
|
||
|
|
DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
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||
|
|
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
|
||
|
|
- | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
|
||
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|
+ | m_GOLDMONT_PLUS | m_INTEL)
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||
|
|
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||
|
|
/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
|
||
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|
DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
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||
|
|
--
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|
|
2.18.2
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