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195 lines
6.2 KiB
195 lines
6.2 KiB
From 348ea6ca54889a2b4006cc71168a173e8182f12e Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Tue, 30 Jan 2024 14:04:38 +0100
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Subject: [PATCH] OvmfPkg/Sec: Setup MTRR early in the boot process.
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RH-Author: Gerd Hoffmann <None>
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RH-MergeRequest: 55: OvmfPkg/Sec: Setup MTRR early in the boot process.
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RH-Jira: RHEL-21704
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Commit: [1/4] c4061788d34f409944898b48642d610c259161f3 (kraxel.rh/centos-src-edk2)
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Specifically before running lzma uncompress of the main firmware volume.
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This is needed to make sure caching is enabled, otherwise the uncompress
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can be extremely slow.
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Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes.
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Background: Depending on virtual machine configuration kvm may uses EPT
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memory types to apply guest MTRR settings. In case MTRRs are disabled
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kvm will use the uncachable memory type for all mappings. The
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vmx_get_mt_mask() function in the linux kernel handles this and can be
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found here:
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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/x86/kvm/vmx/vmx.c?h=v6.7.1#n7580
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In most VM configurations kvm uses MTRR_TYPE_WRBACK unconditionally. In
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case the VM has a mdev device assigned that is not the case though.
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Before commit e8aa4c6546ad ("UefiCpuPkg/ResetVector: Cache Disable
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should not be set by default in CR0") kvm also ended up using
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MTRR_TYPE_WRBACK due to KVM_X86_QUIRK_CD_NW_CLEARED. After that commit
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kvm evaluates guest mtrr settings, which why setting up MTRRs early is
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important now.
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Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Message-ID: <20240130130441.772484-2-kraxel@redhat.com>
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[ kraxel: Downstream-only for now. Timely upstream merge is unlikely
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due to chinese holidays and rhel-9.4 deadlines are close.
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QE regression testing passed. So go with upstream posted
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series v3 ]
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patch_name: edk2-OvmfPkg-Sec-Setup-MTRR-early-in-the-boot-process.patch
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present_in_specfile: true
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location_in_specfile: 49
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---
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OvmfPkg/IntelTdx/Sec/SecMain.c | 32 +++++++++++++++++++++
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OvmfPkg/Library/PlatformInitLib/MemDetect.c | 10 +++----
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OvmfPkg/Sec/SecMain.c | 32 +++++++++++++++++++++
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3 files changed, 69 insertions(+), 5 deletions(-)
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diff --git a/OvmfPkg/IntelTdx/Sec/SecMain.c b/OvmfPkg/IntelTdx/Sec/SecMain.c
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index 4e750755bf..7094d86159 100644
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--- a/OvmfPkg/IntelTdx/Sec/SecMain.c
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+++ b/OvmfPkg/IntelTdx/Sec/SecMain.c
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@@ -26,6 +26,8 @@
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#include <Library/TdxHelperLib.h>
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#include <Library/CcProbeLib.h>
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#include <Library/PeilessStartupLib.h>
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+#include <Register/Intel/ArchitecturalMsr.h>
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+#include <Register/Intel/Cpuid.h>
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#define SEC_IDT_ENTRY_COUNT 34
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@@ -47,6 +49,31 @@ IA32_IDT_GATE_DESCRIPTOR mIdtEntryTemplate = {
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}
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};
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+//
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+// Enable MTRR early, set default type to write back.
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+// Needed to make sure caching is enabled,
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+// without this lzma decompress can be very slow.
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+//
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+STATIC
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+VOID
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+SecMtrrSetup (
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+ VOID
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+ )
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+{
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+ CPUID_VERSION_INFO_EDX Edx;
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+ MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
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+
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+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);
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+ if (!Edx.Bits.MTRR) {
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+ return;
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+ }
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+
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+ DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
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+ DefType.Bits.Type = 6; /* write back */
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+ DefType.Bits.E = 1; /* enable */
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+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
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+}
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+
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VOID
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EFIAPI
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SecCoreStartupWithStack (
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@@ -203,6 +230,11 @@ SecCoreStartupWithStack (
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InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
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DisableApicTimerInterrupt ();
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+ //
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+ // Initialize MTRR
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+ //
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+ SecMtrrSetup ();
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+
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PeilessStartup (&SecCoreData);
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ASSERT (FALSE);
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diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
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index e64c0ee324..b6ba63ef95 100644
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--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
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+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
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@@ -1164,18 +1164,18 @@ PlatformQemuInitializeRam (
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MtrrGetAllMtrrs (&MtrrSettings);
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//
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- // MTRRs disabled, fixed MTRRs disabled, default type is uncached
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+ // See SecMtrrSetup(), default type should be write back
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//
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- ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);
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+ ASSERT ((MtrrSettings.MtrrDefType & BIT11) != 0);
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ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);
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- ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);
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+ ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == MTRR_CACHE_WRITE_BACK);
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//
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// flip default type to writeback
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//
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- SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);
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+ SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, MTRR_CACHE_WRITE_BACK);
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ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);
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- MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;
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+ MtrrSettings.MtrrDefType |= BIT10;
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MtrrSetAllMtrrs (&MtrrSettings);
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//
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diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c
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index 60dfa61842..725b57e2fa 100644
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--- a/OvmfPkg/Sec/SecMain.c
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+++ b/OvmfPkg/Sec/SecMain.c
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@@ -29,6 +29,8 @@
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#include <Ppi/MpInitLibDep.h>
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#include <Library/TdxHelperLib.h>
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#include <Library/CcProbeLib.h>
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+#include <Register/Intel/ArchitecturalMsr.h>
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+#include <Register/Intel/Cpuid.h>
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#include "AmdSev.h"
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#define SEC_IDT_ENTRY_COUNT 34
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@@ -743,6 +745,31 @@ FindAndReportEntryPoints (
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return;
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}
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+//
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+// Enable MTRR early, set default type to write back.
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+// Needed to make sure caching is enabled,
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+// without this lzma decompress can be very slow.
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+//
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+STATIC
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+VOID
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+SecMtrrSetup (
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+ VOID
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+ )
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+{
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+ CPUID_VERSION_INFO_EDX Edx;
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+ MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
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+
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+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);
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+ if (!Edx.Bits.MTRR) {
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+ return;
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+ }
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+
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+ DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
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+ DefType.Bits.Type = 6; /* write back */
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+ DefType.Bits.E = 1; /* enable */
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+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
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+}
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+
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VOID
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EFIAPI
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SecCoreStartupWithStack (
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@@ -942,6 +969,11 @@ SecCoreStartupWithStack (
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InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
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DisableApicTimerInterrupt ();
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+ //
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+ // Initialize MTRR
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+ //
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+ SecMtrrSetup ();
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+
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//
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// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
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//
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