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302 lines
9.3 KiB
302 lines
9.3 KiB
commit 21397732bbcef3347c0d5ff8a0ee5163e803e2fb
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Author: Jeff Law <law@redhat.com>
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Date: Mon Oct 2 12:30:26 2017 -0600
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Dependencies for aarch64 work
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diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
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index 07ff7031b35..91dd5b7fc02 100644
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--- a/gcc/config/aarch64/aarch64-protos.h
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+++ b/gcc/config/aarch64/aarch64-protos.h
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@@ -181,6 +181,7 @@ unsigned aarch64_dbx_register_number (unsigned);
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unsigned aarch64_trampoline_size (void);
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void aarch64_asm_output_labelref (FILE *, const char *);
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void aarch64_elf_asm_named_section (const char *, unsigned, tree);
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+const char * aarch64_output_probe_stack_range (rtx, rtx);
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void aarch64_expand_epilogue (bool);
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void aarch64_expand_mov_immediate (rtx, rtx);
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void aarch64_expand_prologue (void);
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diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
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index 5afc167d569..cadf193cfcf 100644
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--- a/gcc/config/aarch64/aarch64.c
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+++ b/gcc/config/aarch64/aarch64.c
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@@ -969,6 +969,199 @@ aarch64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
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return true;
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}
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+static int
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+aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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+ enum machine_mode mode)
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+{
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+ int i;
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+ unsigned HOST_WIDE_INT val, val2, mask;
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+ int one_match, zero_match;
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+ int num_insns;
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+
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+ val = INTVAL (imm);
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+
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+ if (aarch64_move_imm (val, mode))
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+ {
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+ if (generate)
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+ emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
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+ return 1;
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+ }
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+
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+ /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
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+ (with XXXX non-zero). In that case check to see if the move can be done in
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+ a smaller mode. */
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+ val2 = val & 0xffffffff;
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+ if (mode == DImode
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+ && aarch64_move_imm (val2, SImode)
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+ && (((val >> 32) & 0xffff) == 0 || (val >> 48) == 0))
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+ {
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+ if (generate)
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+ emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val2)));
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+
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+ /* Check if we have to emit a second instruction by checking to see
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+ if any of the upper 32 bits of the original DI mode value is set. */
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+ if (val == val2)
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+ return 1;
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+
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+ i = (val >> 48) ? 48 : 32;
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+
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+ if (generate)
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+ emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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+ GEN_INT ((val >> i) & 0xffff)));
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+
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+ return 2;
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+ }
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+
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+ if ((val >> 32) == 0 || mode == SImode)
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+ {
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+ if (generate)
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+ {
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+ emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val & 0xffff)));
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+ if (mode == SImode)
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+ emit_insn (gen_insv_immsi (dest, GEN_INT (16),
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+ GEN_INT ((val >> 16) & 0xffff)));
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+ else
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+ emit_insn (gen_insv_immdi (dest, GEN_INT (16),
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+ GEN_INT ((val >> 16) & 0xffff)));
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+ }
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+ return 2;
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+ }
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+
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+ /* Remaining cases are all for DImode. */
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+
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+ mask = 0xffff;
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+ zero_match = ((val & mask) == 0) + ((val & (mask << 16)) == 0) +
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+ ((val & (mask << 32)) == 0) + ((val & (mask << 48)) == 0);
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+ one_match = ((~val & mask) == 0) + ((~val & (mask << 16)) == 0) +
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+ ((~val & (mask << 32)) == 0) + ((~val & (mask << 48)) == 0);
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+
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+ if (zero_match != 2 && one_match != 2)
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+ {
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+ /* Try emitting a bitmask immediate with a movk replacing 16 bits.
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+ For a 64-bit bitmask try whether changing 16 bits to all ones or
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+ zeroes creates a valid bitmask. To check any repeated bitmask,
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+ try using 16 bits from the other 32-bit half of val. */
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+
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+ for (i = 0; i < 64; i += 16, mask <<= 16)
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+ {
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+ val2 = val & ~mask;
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+ if (val2 != val && aarch64_bitmask_imm (val2, mode))
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+ break;
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+ val2 = val | mask;
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+ if (val2 != val && aarch64_bitmask_imm (val2, mode))
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+ break;
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+ val2 = val2 & ~mask;
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+ val2 = val2 | (((val2 >> 32) | (val2 << 32)) & mask);
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+ if (val2 != val && aarch64_bitmask_imm (val2, mode))
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+ break;
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+ }
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+ if (i != 64)
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+ {
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+ if (generate)
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+ {
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+ emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val2)));
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+ emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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+ GEN_INT ((val >> i) & 0xffff)));
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+ }
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+ return 2;
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+ }
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+ }
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+
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+ /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
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+ are emitted by the initial mov. If one_match > zero_match, skip set bits,
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+ otherwise skip zero bits. */
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+
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+ num_insns = 1;
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+ mask = 0xffff;
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+ val2 = one_match > zero_match ? ~val : val;
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+ i = (val2 & mask) != 0 ? 0 : (val2 & (mask << 16)) != 0 ? 16 : 32;
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+
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+ if (generate)
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+ emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (one_match > zero_match
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+ ? (val | ~(mask << i))
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+ : (val & (mask << i)))));
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+ for (i += 16; i < 64; i += 16)
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+ {
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+ if ((val2 & (mask << i)) == 0)
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+ continue;
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+ if (generate)
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+ emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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+ GEN_INT ((val >> i) & 0xffff)));
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+ num_insns ++;
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+ }
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+
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+ return num_insns;
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+}
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+
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+/* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
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+ temporary value if necessary. FRAME_RELATED_P should be true if
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+ the RTX_FRAME_RELATED flag should be set and CFA adjustments added
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+ to the generated instructions. If SCRATCHREG is known to hold
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+ abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
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+ immediate again.
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+
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+ Since this function may be used to adjust the stack pointer, we must
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+ ensure that it cannot cause transient stack deallocation (for example
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+ by first incrementing SP and then decrementing when adjusting by a
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+ large immediate). */
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+
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+static void
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+aarch64_add_constant_internal (enum machine_mode mode, int regnum,
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+ int scratchreg, HOST_WIDE_INT delta,
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+ bool frame_related_p, bool emit_move_imm)
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+{
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+ HOST_WIDE_INT mdelta = abs_hwi (delta);
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+ rtx this_rtx = gen_rtx_REG (mode, regnum);
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+ rtx insn;
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+
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+ if (!mdelta)
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+ return;
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+
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+ /* Single instruction adjustment. */
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+ if (aarch64_uimm12_shift (mdelta))
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+ {
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+ insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (delta)));
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+ RTX_FRAME_RELATED_P (insn) = frame_related_p;
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+ return;
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+ }
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+
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+ /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
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+ Only do this if mdelta is not a 16-bit move as adjusting using a move
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+ is better. */
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+ if (mdelta < 0x1000000 && !aarch64_move_imm (mdelta, mode))
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+ {
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+ HOST_WIDE_INT low_off = mdelta & 0xfff;
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+
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+ low_off = delta < 0 ? -low_off : low_off;
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+ insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (low_off)));
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+ RTX_FRAME_RELATED_P (insn) = frame_related_p;
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+ insn = emit_insn (gen_add2_insn (this_rtx, GEN_INT (delta - low_off)));
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+ RTX_FRAME_RELATED_P (insn) = frame_related_p;
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+ return;
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+ }
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+
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+ /* Emit a move immediate if required and an addition/subtraction. */
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+ rtx scratch_rtx = gen_rtx_REG (mode, scratchreg);
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+ if (emit_move_imm)
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+ aarch64_internal_mov_immediate (scratch_rtx, GEN_INT (mdelta), true, mode);
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+ insn = emit_insn (delta < 0 ? gen_sub2_insn (this_rtx, scratch_rtx)
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+ : gen_add2_insn (this_rtx, scratch_rtx));
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+ if (frame_related_p)
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+ {
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+ RTX_FRAME_RELATED_P (insn) = frame_related_p;
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+ rtx adj = plus_constant (mode, this_rtx, delta);
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+ add_reg_note (insn , REG_CFA_ADJUST_CFA,
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+ gen_rtx_SET (VOIDmode, this_rtx, adj));
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+ }
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+}
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+
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+static inline void
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+aarch64_sub_sp (int scratchreg, HOST_WIDE_INT delta, bool frame_related_p)
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+{
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+ aarch64_add_constant_internal (Pmode, SP_REGNUM, scratchreg, -delta,
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+ frame_related_p, true);
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+}
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+
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/* Implement TARGET_PASS_BY_REFERENCE. */
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static bool
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@@ -1476,6 +1669,47 @@ aarch64_libgcc_cmp_return_mode (void)
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return SImode;
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}
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+#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
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+
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+/* We use the 12-bit shifted immediate arithmetic instructions so values
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+ must be multiple of (1 << 12), i.e. 4096. */
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+#define ARITH_FACTOR 4096
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+
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+/* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
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+ absolute addresses. */
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+
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+const char *
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+aarch64_output_probe_stack_range (rtx reg1, rtx reg2)
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+{
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+ static int labelno = 0;
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+ char loop_lab[32];
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+ rtx xops[2];
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+
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+ ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
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+
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+ /* Loop. */
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+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
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+
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+ /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
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+ xops[0] = reg1;
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+ xops[1] = GEN_INT (PROBE_INTERVAL);
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+ output_asm_insn ("sub\t%0, %0, %1", xops);
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+
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+ /* Probe at TEST_ADDR. */
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+ output_asm_insn ("str\txzr, [%0]", xops);
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+
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+ /* Test if TEST_ADDR == LAST_ADDR. */
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+ xops[1] = reg2;
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+ output_asm_insn ("cmp\t%0, %1", xops);
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+
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+ /* Branch. */
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+ fputs ("\tb.ne\t", asm_out_file);
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+ assemble_name_raw (asm_out_file, loop_lab);
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+ fputc ('\n', asm_out_file);
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+
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+ return "";
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+}
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+
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static bool
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aarch64_frame_pointer_required (void)
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{
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diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
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index 91299901bbf..17082486ac8 100644
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--- a/gcc/config/aarch64/aarch64.md
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+++ b/gcc/config/aarch64/aarch64.md
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@@ -88,6 +88,7 @@
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UNSPEC_ST4
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UNSPEC_TLS
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UNSPEC_TLSDESC
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+ UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing.
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UNSPEC_VSTRUCTDUMMY
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])
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@@ -3399,6 +3400,18 @@
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[(set_attr "length" "0")]
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)
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+(define_insn "probe_stack_range"
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+ [(set (match_operand:DI 0 "register_operand" "=r")
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+ (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")
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+ (match_operand:DI 2 "register_operand" "r")]
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+ UNSPECV_PROBE_STACK_RANGE))]
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+ ""
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+{
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+ return aarch64_output_probe_stack_range (operands[0], operands[2]);
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+}
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+ [(set_attr "length" "32")]
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+)
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+
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;; Named pattern for expanding thread pointer reference.
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(define_expand "get_thread_pointerdi"
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[(match_operand:DI 0 "register_operand" "=r")]
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