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70 lines
3.9 KiB
70 lines
3.9 KiB
3 years ago
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diff -up chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp.gcc12fix chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp
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--- chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp.gcc12fix 2022-02-25 22:17:18.071775686 +0000
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+++ chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.cpp 2022-02-25 22:17:40.964996468 +0000
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@@ -659,6 +659,7 @@ void emitIASOpTyGPR(const Cfg *Func, Typ
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}
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}
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+#if 0
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template <bool VarCanBeByte, bool SrcCanBeByte>
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void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var,
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const Operand *Src, const GPREmitterRegOp &Emitter) {
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@@ -697,6 +698,7 @@ void emitIASRegOpTyGPR(const Cfg *Func,
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llvm_unreachable("Unexpected operand type");
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}
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}
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+#endif
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void emitIASAddrOpTyGPR(const Cfg *Func, Type Ty, const AsmAddress &Addr,
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const Operand *Src, const GPREmitterAddrOp &Emitter) {
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diff -up chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h.gcc12fix chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h
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--- chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h.gcc12fix 2022-02-25 22:17:51.409640955 +0000
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+++ chromium-98.0.4758.102/third_party/swiftshader/third_party/subzero/src/IceInstX8664.h 2022-02-25 22:19:13.478847553 +0000
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@@ -576,8 +576,44 @@ void emitIASXmmShift(const Cfg *Func, Ty
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/// Emit a two-operand (GPR) instruction, where the dest operand is a Variable
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/// that's guaranteed to be a register.
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template <bool VarCanBeByte = true, bool SrcCanBeByte = true>
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-void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Dst,
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- const Operand *Src, const GPREmitterRegOp &Emitter);
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+
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+void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var,
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+ const Operand *Src, const GPREmitterRegOp &Emitter) {
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+ auto *Target = InstX86Base::getTarget(Func);
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+ Assembler *Asm = Func->getAssembler<Assembler>();
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+ assert(Var->hasReg());
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+ // We cheat a little and use GPRRegister even for byte operations.
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+ GPRRegister VarReg = VarCanBeByte ? RegX8664::getEncodedGPR(Var->getRegNum())
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+ : RegX8664::getEncodedGPR(Var->getRegNum());
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+ if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
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+ if (SrcVar->hasReg()) {
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+ GPRRegister SrcReg = SrcCanBeByte
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+ ? RegX8664::getEncodedGPR(SrcVar->getRegNum())
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+ : RegX8664::getEncodedGPR(SrcVar->getRegNum());
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+ (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
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+ } else {
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+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
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+ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
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+ }
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+ } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
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+ Mem->emitSegmentOverride(Asm);
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+ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
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+ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
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+ (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
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+ } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
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+ assert(Utils::IsInt(32, Imm->getValue()));
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+ (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
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+ } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
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+ const auto FixupKind = (Reloc->getName().hasStdString() &&
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+ Reloc->getName().toString() == GlobalOffsetTable)
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+ ? FK_GotPC
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+ : FK_Abs;
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+ AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
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+ (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Fixup));
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+ } else {
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+ llvm_unreachable("Unexpected operand type");
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+ }
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+}
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/// Instructions of the form x := op(x).
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template <typename InstX86Base::InstKindX86 K>
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