parent
5da80e5751
commit
452d6a0a36
@ -1 +1,2 @@
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2dd8d1ce34dc7b1cb2073123e30c4901221835b0 SOURCES/binutils-2.35.2.tar.xz
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2dd8d1ce34dc7b1cb2073123e30c4901221835b0 SOURCES/binutils-2.35.2.tar.xz
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d57616dc8475c78a107762aa8fcee9336ab6e40f SOURCES/binutils.unicode.patch
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@ -1 +1,2 @@
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SOURCES/binutils-2.35.2.tar.xz
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SOURCES/binutils-2.35.2.tar.xz
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SOURCES/binutils.unicode.patch
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@ -0,0 +1,34 @@
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--- binutils.orig/binutils/objdump.c 2023-03-03 11:37:39.209614222 +0000
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+++ binutils-2.35.2/binutils/objdump.c 2023-03-03 11:39:45.492428807 +0000
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@@ -1090,20 +1090,19 @@ compare_symbols (const void *ap, const v
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return 1;
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}
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- if (bfd_get_flavour (bfd_asymbol_bfd (a)) == bfd_target_elf_flavour
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+ /* Sort larger size ELF symbols before smaller. See PR20337. */
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+ bfd_vma asz = 0;
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+ if ((a->flags & (BSF_SECTION_SYM | BSF_SYNTHETIC)) == 0
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+ && bfd_get_flavour (bfd_asymbol_bfd (a)) == bfd_target_elf_flavour)
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+ asz = ((elf_symbol_type *) a)->internal_elf_sym.st_size;
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+
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+ bfd_vma bsz = 0;
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+ if ((b->flags & (BSF_SECTION_SYM | BSF_SYNTHETIC)) == 0
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&& bfd_get_flavour (bfd_asymbol_bfd (b)) == bfd_target_elf_flavour)
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- {
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- bfd_vma asz, bsz;
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+ bsz = ((elf_symbol_type *) b)->internal_elf_sym.st_size;
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- asz = 0;
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- if ((a->flags & (BSF_SECTION_SYM | BSF_SYNTHETIC)) == 0)
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- asz = ((elf_symbol_type *) a)->internal_elf_sym.st_size;
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- bsz = 0;
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- if ((b->flags & (BSF_SECTION_SYM | BSF_SYNTHETIC)) == 0)
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- bsz = ((elf_symbol_type *) b)->internal_elf_sym.st_size;
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- if (asz != bsz)
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- return asz > bsz ? -1 : 1;
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- }
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+ if (asz != bsz)
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+ return asz > bsz ? -1 : 1;
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/* Symbols that start with '.' might be section names, so sort them
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after symbols that don't start with '.'. */
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@ -0,0 +1,152 @@
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diff -rup binutils.orig/gas/NEWS binutils-2.35.2/gas/NEWS
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--- binutils.orig/gas/NEWS 2023-04-26 11:29:49.525097847 +0100
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+++ binutils-2.35.2/gas/NEWS 2023-04-26 11:30:59.811955065 +0100
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@@ -1,5 +1,7 @@
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-*- text -*-
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+* Add support for +flagm feature for -march in Armv8.4 AArch64.
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+
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* Add support for Intel AMX instructions.
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* Add {disp16} pseudo prefix to x86 assembler.
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diff -rup binutils.orig/gas/config/tc-aarch64.c binutils-2.35.2/gas/config/tc-aarch64.c
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--- binutils.orig/gas/config/tc-aarch64.c 2023-04-26 11:29:48.944099025 +0100
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+++ binutils-2.35.2/gas/config/tc-aarch64.c 2023-04-26 11:31:42.994864009 +0100
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@@ -9080,6 +9080,8 @@ static const struct aarch64_option_cpu_v
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AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
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{"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
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+ {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0),
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+ AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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diff -rup binutils.orig/gas/doc/c-aarch64.texi binutils-2.35.2/gas/doc/c-aarch64.texi
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--- binutils.orig/gas/doc/c-aarch64.texi 2023-04-26 11:29:48.881099153 +0100
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+++ binutils-2.35.2/gas/doc/c-aarch64.texi 2023-04-26 11:32:22.402780914 +0100
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@@ -222,6 +222,8 @@ automatically cause those extensions to
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@code{pmullt} and @code{pmullb} instructions.
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@item @code{sve2-sha3} @tab ARMv8-A @tab No
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@tab Enable SVE2 SHA3 Extension.
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+@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
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+ @tab Enable Flag Manipulation instructions.
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@end multitable
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@node AArch64 Syntax
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diff -rup binutils.orig/include/opcode/aarch64.h binutils-2.35.2/include/opcode/aarch64.h
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--- binutils.orig/include/opcode/aarch64.h 2023-04-26 11:29:48.702099517 +0100
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+++ binutils-2.35.2/include/opcode/aarch64.h 2023-04-26 11:35:17.346412224 +0100
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@@ -69,7 +69,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
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#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
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#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
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-#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
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+#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* v8.5 Flag Manipulation version 2. */
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#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
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#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
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#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
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@@ -84,6 +84,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
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#define AARCH64_FEATURE_F32MM (1ULL << 53)
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#define AARCH64_FEATURE_F64MM (1ULL << 54)
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+#define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */
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/* Crypto instructions are the combination of AES and SHA2. */
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#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
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@@ -109,6 +110,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
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AARCH64_FEATURE_V8_4 \
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| AARCH64_FEATURE_DOTPROD \
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+ | AARCH64_FEATURE_FLAGM \
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| AARCH64_FEATURE_F16_FML)
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#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
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AARCH64_FEATURE_V8_5 \
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diff -rup binutils.orig/opcodes/aarch64-tbl.h binutils-2.35.2/opcodes/aarch64-tbl.h
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--- binutils.orig/opcodes/aarch64-tbl.h 2023-04-26 11:29:48.705099511 +0100
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+++ binutils-2.35.2/opcodes/aarch64-tbl.h 2023-04-26 11:37:27.299161621 +0100
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@@ -2406,6 +2406,8 @@ static const aarch64_feature_set aarch64
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static const aarch64_feature_set aarch64_feature_f64mm_sve =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F64MM
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| AARCH64_FEATURE_SVE, 0);
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+static const aarch64_feature_set aarch64_feature_flagm =
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+ AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0);
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#define CORE &aarch64_feature_v8
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@@ -2450,6 +2452,7 @@ static const aarch64_feature_set aarch64
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#define F32MM_SVE &aarch64_feature_f32mm_sve
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#define F64MM_SVE &aarch64_feature_f64mm_sve
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#define I8MM &aarch64_feature_i8mm
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+#define FLAGM &aarch64_feature_flagm
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#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
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@@ -2553,6 +2556,8 @@ static const aarch64_feature_set aarch64
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{ NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
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#define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
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{ NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
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+#define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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+ { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL }
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struct aarch64_opcode aarch64_opcode_table[] =
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{
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@@ -3865,7 +3870,7 @@ struct aarch64_opcode aarch64_opcode_tab
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potentially alias with too many instructions and so the tree can't be constructed. As a work
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around we just place cfinv before msr. This means the order between these two shouldn't be
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changed. */
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- V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
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+ FLAGM_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
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CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
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CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
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CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
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@@ -5043,9 +5048,9 @@ struct aarch64_opcode aarch64_opcode_tab
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FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
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FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
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/* System extensions ARMv8.4-a. */
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- V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
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- V8_4_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
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- V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
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+ FLAGM_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
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+ FLAGM_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
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+ FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
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/* Memory access instructions ARMv8.4-a. */
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V8_4_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
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V8_4_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
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--- /dev/null 2023-04-26 09:16:03.694889721 +0100
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+++ binutils-2.35.2/gas/testsuite/gas/aarch64/flagm.d 2023-04-26 11:33:08.910682842 +0100
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@@ -0,0 +1,16 @@
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+#name: FLAGM (Condition flag manipulation) feature
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+#objdump: -dr
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+
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+.*: file format .*
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+
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+Disassembly of section \.text:
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+
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+0+ <.*>:
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+.*: d500401f cfinv
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+.*: ba0407cf rmif x30, #8, #15
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+.*: 3a00080d setf8 w0
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+.*: 3a00480d setf16 w0
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+.*: d500401f cfinv
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+.*: ba0407cf rmif x30, #8, #15
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+.*: 3a00080d setf8 w0
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+.*: 3a00480d setf16 w0
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--- /dev/null 2023-04-26 09:16:03.694889721 +0100
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+++ binutils-2.35.2/gas/testsuite/gas/aarch64/flagm.s 2023-04-26 11:39:10.597962432 +0100
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@@ -0,0 +1,16 @@
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+/* FLAGM (Condition flag manipulation) feature from Armv8.4-A. */
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+.arch armv8.4-a
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+
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+ cfinv
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+ rmif x30, #8, #15
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+ setf8 w0
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+ setf16 w0
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+
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+
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+/* FLAGM feature enabled with +flagm. */
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+.arch armv8-a+flagm
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+
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+ cfinv
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+ rmif x30, #8, #15
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+ setf8 w0
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+ setf16 w0
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@ -0,0 +1,17 @@
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|
diff --git a/bfd/elf.c b/bfd/elf.c
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index fe00e0f9189..7cd7febcf95 100644
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|
--- a/bfd/elf.c
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|
+++ b/bfd/elf.c
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|
@@ -8918,7 +8918,9 @@ _bfd_elf_slurp_version_tables (bfd *abfd, bool default_imported_symver)
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|
bfd_set_error (bfd_error_file_too_big);
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|
goto error_return_verref;
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|
}
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|
- elf_tdata (abfd)->verref = (Elf_Internal_Verneed *) bfd_alloc (abfd, amt);
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|
+ if (amt == 0)
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|
+ goto error_return_verref;
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|
+ elf_tdata (abfd)->verref = (Elf_Internal_Verneed *) bfd_zalloc (abfd, amt);
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|
if (elf_tdata (abfd)->verref == NULL)
|
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|
goto error_return_verref;
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|
|
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|
--
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|
2.31.1
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in new issue