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import binutils-2.41-51.el10

Browse Source
cs10 imports/cs10/binutils-2.41-51.el10
MSVSphere Packaging Team 2 months ago
parent d38c88d975
commit 0550aab309
Signed by: sys_gitsync
GPG Key ID: B2B0B9F29E528FE8
18 changed files with 3471 additions and 9 deletions
Show Stats Download Patch File Download Diff File

74
SOURCES/binutils-aarch64-RELR.patch
Unescape View File

@ -3446,3 +3446,77 @@ Only in binutils-2.41/ld/testsuite/ld-aarch64: relr-discard.s
return _bfd_final_link_relocate (howto, input_bfd, input_section,
contents, rel->r_offset, value,
signed_addend);
diff -rup binutils.orig/ld/testsuite/ld-aarch64/relr-align.d binutils-2.41/ld/testsuite/ld-aarch64/relr-align.d
--- binutils.orig/ld/testsuite/ld-aarch64/relr-align.d 2024-12-02 18:36:21.957480121 +0000
+++ binutils-2.41/ld/testsuite/ld-aarch64/relr-align.d 2024-12-02 18:37:32.142592796 +0000
@@ -2,13 +2,13 @@
#ld: -shared -z pack-relative-relocs -T relocs.ld
#readelf: -rW
-Relocation section '\.rela\.dyn' at offset 0x10090 contains 3 entries:
+Relocation section '\.rela\.dyn' at offset 0x100.. contains 3 entries:
Offset Info Type Symbol's Value Symbol's Name \+ Addend
0000000012340011 0000000000000403 R_AARCH64_RELATIVE 10000
0000000012340019 0000000000000403 R_AARCH64_RELATIVE 10000
0000000012340041 0000000000000403 R_AARCH64_RELATIVE 10000
-Relocation section '\.relr\.dyn' at offset 0x100d8 contains 9 entries which relocate 10 locations:
+Relocation section '\.relr\.dyn' at offset 0x100.. contains 9 entries which relocate 10 locations:
Index: Entry Address Symbolic Address
0000: 0000000012340000 0000000012340000 double_0
0001: 0000000000000003 0000000012340008 double_0 \+ 0x8
diff -rup binutils.orig/ld/testsuite/ld-aarch64/relr-data-shared.d binutils-2.41/ld/testsuite/ld-aarch64/relr-data-shared.d
--- binutils.orig/ld/testsuite/ld-aarch64/relr-data-shared.d 2024-12-02 18:36:21.957480121 +0000
+++ binutils-2.41/ld/testsuite/ld-aarch64/relr-data-shared.d 2024-12-02 18:37:58.702635434 +0000
@@ -2,7 +2,7 @@
#ld: -shared -z pack-relative-relocs -T relocs.ld
#readelf: -rW
-Relocation section '\.rela\.dyn' at offset 0x10150 contains 6 entries:
+Relocation section '\.rela\.dyn' at offset 0x101.. contains 6 entries:
Offset Info Type Symbol's Value Symbol's Name \+ Addend
0000000012340000 0000000000000403 R_AARCH64_RELATIVE 10004
0000000012340008 0000000000000403 R_AARCH64_RELATIVE 10008
@@ -11,7 +11,7 @@ Relocation section '\.rela\.dyn' at offs
0000000012340030 0000000400000101 R_AARCH64_ABS64 000000000001000c sym_global \+ 0
0000000012340040 0000000300000101 R_AARCH64_ABS64 0000000000000000 sym_weak_undef \+ 0
-Relocation section '\.relr\.dyn' at offset 0x101e0 contains 2 entries which relocate 3 locations:
+Relocation section '\.relr\.dyn' at offset 0x101.. contains 2 entries which relocate 3 locations:
Index: Entry Address Symbolic Address
0000: 0000000012340020 0000000012340020 aligned_local
0001: 0000000000000023 0000000012340028 aligned_hidden
diff -rup binutils.orig/ld/testsuite/ld-aarch64/relr-got-shared.d binutils-2.41/ld/testsuite/ld-aarch64/relr-got-shared.d
--- binutils.orig/ld/testsuite/ld-aarch64/relr-got-shared.d 2024-12-02 18:36:21.957480121 +0000
+++ binutils-2.41/ld/testsuite/ld-aarch64/relr-got-shared.d 2024-12-02 18:38:21.422671912 +0000
@@ -2,13 +2,13 @@
#ld: -shared -z pack-relative-relocs -T relocs.ld
#readelf: -rW
-Relocation section '\.rela\.dyn' at offset 0x10168 contains 3 entries:
+Relocation section '\.rela\.dyn' at offset 0x101.. contains 3 entries:
Offset Info Type Symbol's Value Symbol's Name \+ Addend
0000000000020020 0000000300000401 R_AARCH64_GLOB_DAT 0000000000010038 sym_global \+ 0
0000000000020028 0000000500000401 R_AARCH64_GLOB_DAT 000000000000002a sym_global_abs \+ 0
0000000000020030 0000000200000401 R_AARCH64_GLOB_DAT 0000000000000000 sym_weak_undef \+ 0
-Relocation section '\.relr\.dyn' at offset 0x101b0 contains 2 entries which relocate 3 locations:
+Relocation section '\.relr\.dyn' at offset 0x101.. contains 2 entries which relocate 3 locations:
Index: Entry Address Symbolic Address
0000: 0000000000020008 0000000000020008 _GLOBAL_OFFSET_TABLE_ \+ 0x8
0001: 0000000000000007 0000000000020010 _GLOBAL_OFFSET_TABLE_ \+ 0x10
--- binutils.orig/ld/testsuite/ld-aarch64/relr-text-shared.d 2024-12-02 18:36:21.957480121 +0000
+++ binutils-2.41/ld/testsuite/ld-aarch64/relr-text-shared.d 2024-12-02 19:05:37.138237202 +0000
@@ -5,10 +5,10 @@
#...
0x0000000000000016 \(TEXTREL\) 0x0
#...
- 0x0000000000000024 \(RELR\) 0x10098
+ 0x0000000000000024 \(RELR\) 0x100..
0x0000000000000023 \(RELRSZ\) 8 \(bytes\)
0x0000000000000025 \(RELRENT\) 8 \(bytes\)
#...
-Relocation section '.relr.dyn' at offset 0x10098 contains 1 entry which relocates 1 location:
+Relocation section '.relr.dyn' at offset 0x100.. contains 1 entry which relocates 1 location:
Index: Entry Address Symbolic Address
0000: 0000000000010000 0000000000010000 _start

656
SOURCES/binutils-s390-arch15-part-01.patch
Unescape View File

@ -0,0 +1,656 @@
From 9c422a59953cd6b64bc8ed5f3d6e72a180f13540 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 23 Nov 2023 15:43:36 +0100
Subject: [PATCH] s390: Position independent verification of relative addressing
Commit: c62bc28b2155
Opcode test cases for z/Architecture instructions that use relative
addressing contained hardcoded offsets in the test verification
patterns. Inserting or reordering of instructions into those test cases
therefore required updating of those hardcoded offsets.
Use regular expressions with backreferences to verify results of test
cases containing instructions with relative addressing. This makes the
verification position independent.
gas/
* testsuite/gas/s390/esa-g5.d: Make opcode test verification
pattern position independent where possible.
* testsuite/gas/s390/esa-z900.d: Likewise.
* testsuite/gas/s390/zarch-z900.d: Likewise.
* testsuite/gas/s390/zarch-z10.d: Likewise.
* testsuite/gas/s390/zarch-z196.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
gas/testsuite/gas/s390/esa-g5.d | 104 +++++------
gas/testsuite/gas/s390/esa-z900.d | 96 +++++-----
gas/testsuite/gas/s390/zarch-z10.d | 254 +++++++++++++--------------
gas/testsuite/gas/s390/zarch-z196.d | 2 +-
gas/testsuite/gas/s390/zarch-z900.d | 12 +-
gas/testsuite/gas/s390/zarch-zEC12.d | 6 +-
6 files changed, 237 insertions(+), 237 deletions(-)
diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 67a971bef15..7422e88b127 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -77,15 +77,15 @@ Disassembly of section .text:
.*: 47 25 af ff [ ]*bh 4095\(%r5,%r10\)
.*: 07 29 [ ]*bhr %r9
.*: 07 f9 [ ]*br %r9
-.*: a7 95 00 00 [ ]*bras %r9,e2 <foo\+0xe2>
-.*: a7 65 00 00 [ ]*bras %r6,e6 <foo\+0xe6>
-.*: a7 64 00 00 [ ]*jlh ea <foo\+0xea>
-.*: a7 66 00 00 [ ]*brct %r6,ee <foo\+0xee>
-.*: a7 66 00 00 [ ]*brct %r6,f2 <foo\+0xf2>
-.*: 84 69 00 00 [ ]*brxh %r6,%r9,f6 <foo\+0xf6>
-.*: 84 69 00 00 [ ]*brxh %r6,%r9,fa <foo\+0xfa>
-.*: 85 69 00 00 [ ]*brxle %r6,%r9,fe <foo\+0xfe>
-.*: 85 69 00 00 [ ]*brxle %r6,%r9,102 <foo\+0x102>
+ *([\da-f]+): a7 95 00 00 [ ]*bras %r9,\1 <foo\+0x\1>
+ *([\da-f]+): a7 65 00 00 [ ]*bras %r6,\1 <foo\+0x\1>
+ *([\da-f]+): a7 64 00 00 [ ]*jlh \1 <foo\+0x\1>
+ *([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 <foo\+0x\1>
+ *([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 <foo\+0x\1>
+ *([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 <foo\+0x\1>
+ *([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 <foo\+0x\1>
+ *([\da-f]+): 85 69 00 00 [ ]*brxle %r6,%r9,\1 <foo\+0x\1>
+ *([\da-f]+): 85 69 00 00 [ ]*brxle %r6,%r9,\1 <foo\+0x\1>
.*: b2 5a 00 69 [ ]*bsa %r6,%r9
.*: b2 58 00 69 [ ]*bsg %r6,%r9
.*: 0b 69 [ ]*bsm %r6,%r9
@@ -184,49 +184,49 @@ Disassembly of section .text:
.*: b2 21 00 69 [ ]*ipte %r6,%r9
.*: b2 29 00 69 [ ]*iske %r6,%r9
.*: b2 23 00 69 [ ]*ivsk %r6,%r9
-.*: a7 f4 00 00 [ ]*j 288 <foo\+0x288>
-.*: a7 84 00 00 [ ]*je 28c <foo\+0x28c>
-.*: a7 24 00 00 [ ]*jh 290 <foo\+0x290>
-.*: a7 a4 00 00 [ ]*jhe 294 <foo\+0x294>
-.*: a7 44 00 00 [ ]*jl 298 <foo\+0x298>
-.*: a7 c4 00 00 [ ]*jle 29c <foo\+0x29c>
-.*: a7 64 00 00 [ ]*jlh 2a0 <foo\+0x2a0>
-.*: a7 44 00 00 [ ]*jl 2a4 <foo\+0x2a4>
-.*: a7 74 00 00 [ ]*jne 2a8 <foo\+0x2a8>
-.*: a7 d4 00 00 [ ]*jnh 2ac <foo\+0x2ac>
-.*: a7 54 00 00 [ ]*jnhe 2b0 <foo\+0x2b0>
-.*: a7 b4 00 00 [ ]*jnl 2b4 <foo\+0x2b4>
-.*: a7 34 00 00 [ ]*jnle 2b8 <foo\+0x2b8>
-.*: a7 94 00 00 [ ]*jnlh 2bc <foo\+0x2bc>
-.*: a7 b4 00 00 [ ]*jnl 2c0 <foo\+0x2c0>
-.*: a7 e4 00 00 [ ]*jno 2c4 <foo\+0x2c4>
-.*: a7 d4 00 00 [ ]*jnh 2c8 <foo\+0x2c8>
-.*: a7 74 00 00 [ ]*jne 2cc <foo\+0x2cc>
-.*: a7 14 00 00 [ ]*jo 2d0 <foo\+0x2d0>
-.*: a7 24 00 00 [ ]*jh 2d4 <foo\+0x2d4>
-.*: a7 84 00 00 [ ]*je 2d8 <foo\+0x2d8>
-.*: a7 04 00 00 [ ]*jnop 2dc <foo\+0x2dc>
-.*: a7 14 00 00 [ ]*jo 2e0 <foo\+0x2e0>
-.*: a7 24 00 00 [ ]*jh 2e4 <foo\+0x2e4>
-.*: a7 24 00 00 [ ]*jh 2e8 <foo\+0x2e8>
-.*: a7 34 00 00 [ ]*jnle 2ec <foo\+0x2ec>
-.*: a7 44 00 00 [ ]*jl 2f0 <foo\+0x2f0>
-.*: a7 44 00 00 [ ]*jl 2f4 <foo\+0x2f4>
-.*: a7 54 00 00 [ ]*jnhe 2f8 <foo\+0x2f8>
-.*: a7 64 00 00 [ ]*jlh 2fc <foo\+0x2fc>
-.*: a7 74 00 00 [ ]*jne 300 <foo\+0x300>
-.*: a7 74 00 00 [ ]*jne 304 <foo\+0x304>
-.*: a7 84 00 00 [ ]*je 308 <foo\+0x308>
-.*: a7 84 00 00 [ ]*je 30c <foo\+0x30c>
-.*: a7 94 00 00 [ ]*jnlh 310 <foo\+0x310>
-.*: a7 a4 00 00 [ ]*jhe 314 <foo\+0x314>
-.*: a7 b4 00 00 [ ]*jnl 318 <foo\+0x318>
-.*: a7 b4 00 00 [ ]*jnl 31c <foo\+0x31c>
-.*: a7 c4 00 00 [ ]*jle 320 <foo\+0x320>
-.*: a7 d4 00 00 [ ]*jnh 324 <foo\+0x324>
-.*: a7 d4 00 00 [ ]*jnh 328 <foo\+0x328>
-.*: a7 e4 00 00 [ ]*jno 32c <foo\+0x32c>
-.*: a7 f4 00 00 [ ]*j 330 <foo\+0x330>
+ *([\da-f]+): a7 f4 00 00 [ ]*j \1 <foo\+0x\1>
+ *([\da-f]+): a7 84 00 00 [ ]*je \1 <foo\+0x\1>
+ *([\da-f]+): a7 24 00 00 [ ]*jh \1 <foo\+0x\1>
+ *([\da-f]+): a7 a4 00 00 [ ]*jhe \1 <foo\+0x\1>
+ *([\da-f]+): a7 44 00 00 [ ]*jl \1 <foo\+0x\1>
+ *([\da-f]+): a7 c4 00 00 [ ]*jle \1 <foo\+0x\1>
+ *([\da-f]+): a7 64 00 00 [ ]*jlh \1 <foo\+0x\1>
+ *([\da-f]+): a7 44 00 00 [ ]*jl \1 <foo\+0x\1>
+ *([\da-f]+): a7 74 00 00 [ ]*jne \1 <foo\+0x\1>
+ *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 <foo\+0x\1>
+ *([\da-f]+): a7 54 00 00 [ ]*jnhe \1 <foo\+0x\1>
+ *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 <foo\+0x\1>
+ *([\da-f]+): a7 34 00 00 [ ]*jnle \1 <foo\+0x\1>
+ *([\da-f]+): a7 94 00 00 [ ]*jnlh \1 <foo\+0x\1>
+ *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 <foo\+0x\1>
+ *([\da-f]+): a7 e4 00 00 [ ]*jno \1 <foo\+0x\1>
+ *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 <foo\+0x\1>
+ *([\da-f]+): a7 74 00 00 [ ]*jne \1 <foo\+0x\1>
+ *([\da-f]+): a7 14 00 00 [ ]*jo \1 <foo\+0x\1>
+ *([\da-f]+): a7 24 00 00 [ ]*jh \1 <foo\+0x\1>
+ *([\da-f]+): a7 84 00 00 [ ]*je \1 <foo\+0x\1>
+ *([\da-f]+): a7 04 00 00 [ ]*jnop \1 <foo\+0x\1>
+ *([\da-f]+): a7 14 00 00 [ ]*jo \1 <foo\+0x\1>
+ *([\da-f]+): a7 24 00 00 [ ]*jh \1 <foo\+0x\1>
+ *([\da-f]+): a7 24 00 00 [ ]*jh \1 <foo\+0x\1>
+ *([\da-f]+): a7 34 00 00 [ ]*jnle \1 <foo\+0x\1>
+ *([\da-f]+): a7 44 00 00 [ ]*jl \1 <foo\+0x\1>
+ *([\da-f]+): a7 44 00 00 [ ]*jl \1 <foo\+0x\1>
+ *([\da-f]+): a7 54 00 00 [ ]*jnhe \1 <foo\+0x\1>
+ *([\da-f]+): a7 64 00 00 [ ]*jlh \1 <foo\+0x\1>
+ *([\da-f]+): a7 74 00 00 [ ]*jne \1 <foo\+0x\1>
+ *([\da-f]+): a7 74 00 00 [ ]*jne \1 <foo\+0x\1>
+ *([\da-f]+): a7 84 00 00 [ ]*je \1 <foo\+0x\1>
+ *([\da-f]+): a7 84 00 00 [ ]*je \1 <foo\+0x\1>
+ *([\da-f]+): a7 94 00 00 [ ]*jnlh \1 <foo\+0x\1>
+ *([\da-f]+): a7 a4 00 00 [ ]*jhe \1 <foo\+0x\1>
+ *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 <foo\+0x\1>
+ *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 <foo\+0x\1>
+ *([\da-f]+): a7 c4 00 00 [ ]*jle \1 <foo\+0x\1>
+ *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 <foo\+0x\1>
+ *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 <foo\+0x\1>
+ *([\da-f]+): a7 e4 00 00 [ ]*jno \1 <foo\+0x\1>
+ *([\da-f]+): a7 f4 00 00 [ ]*j \1 <foo\+0x\1>
.*: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\)
.*: b3 18 00 69 [ ]*kdbr %f6,%f9
.*: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\)
diff --git a/gas/testsuite/gas/s390/esa-z900.d b/gas/testsuite/gas/s390/esa-z900.d
index 86db0641e95..75e3a385815 100644
--- a/gas/testsuite/gas/s390/esa-z900.d
+++ b/gas/testsuite/gas/s390/esa-z900.d
@@ -7,53 +7,53 @@ Disassembly of section .text:
.* <foo>:
.*: c0 f4 00 00 00 00 [ ]*jg 0 <foo>
-.*: c0 04 00 00 00 00 [ ]*jgnop 6 <foo\+0x6>
-.*: c0 14 00 00 00 00 [ ]*jgo c <foo\+0xc>
-.*: c0 24 00 00 00 00 [ ]*jgh 12 <foo\+0x12>
-.*: c0 24 00 00 00 00 [ ]*jgh 18 <foo\+0x18>
-.*: c0 34 00 00 00 00 [ ]*jgnle 1e <foo\+0x1e>
-.*: c0 44 00 00 00 00 [ ]*jgl 24 <foo\+0x24>
-.*: c0 44 00 00 00 00 [ ]*jgl 2a <foo\+0x2a>
-.*: c0 54 00 00 00 00 [ ]*jgnhe 30 <foo\+0x30>
-.*: c0 64 00 00 00 00 [ ]*jglh 36 <foo\+0x36>
-.*: c0 74 00 00 00 00 [ ]*jgne 3c <foo\+0x3c>
-.*: c0 74 00 00 00 00 [ ]*jgne 42 <foo\+0x42>
-.*: c0 84 00 00 00 00 [ ]*jge 48 <foo\+0x48>
-.*: c0 84 00 00 00 00 [ ]*jge 4e <foo\+0x4e>
-.*: c0 94 00 00 00 00 [ ]*jgnlh 54 <foo\+0x54>
-.*: c0 a4 00 00 00 00 [ ]*jghe 5a <foo\+0x5a>
-.*: c0 b4 00 00 00 00 [ ]*jgnl 60 <foo\+0x60>
-.*: c0 b4 00 00 00 00 [ ]*jgnl 66 <foo\+0x66>
-.*: c0 c4 00 00 00 00 [ ]*jgle 6c <foo\+0x6c>
-.*: c0 d4 00 00 00 00 [ ]*jgnh 72 <foo\+0x72>
-.*: c0 d4 00 00 00 00 [ ]*jgnh 78 <foo\+0x78>
-.*: c0 e4 00 00 00 00 [ ]*jgno 7e <foo\+0x7e>
-.*: c0 f4 00 00 00 00 [ ]*jg 84 <foo\+0x84>
-.*: c0 14 00 00 00 00 [ ]*jgo 8a <foo\+0x8a>
-.*: c0 24 00 00 00 00 [ ]*jgh 90 <foo\+0x90>
-.*: c0 24 00 00 00 00 [ ]*jgh 96 <foo\+0x96>
-.*: c0 34 00 00 00 00 [ ]*jgnle 9c <foo\+0x9c>
-.*: c0 44 00 00 00 00 [ ]*jgl a2 <foo\+0xa2>
-.*: c0 44 00 00 00 00 [ ]*jgl a8 <foo\+0xa8>
-.*: c0 54 00 00 00 00 [ ]*jgnhe ae <foo\+0xae>
-.*: c0 64 00 00 00 00 [ ]*jglh b4 <foo\+0xb4>
-.*: c0 74 00 00 00 00 [ ]*jgne ba <foo\+0xba>
-.*: c0 74 00 00 00 00 [ ]*jgne c0 <foo\+0xc0>
-.*: c0 84 00 00 00 00 [ ]*jge c6 <foo\+0xc6>
-.*: c0 84 00 00 00 00 [ ]*jge cc <foo\+0xcc>
-.*: c0 94 00 00 00 00 [ ]*jgnlh d2 <foo\+0xd2>
-.*: c0 a4 00 00 00 00 [ ]*jghe d8 <foo\+0xd8>
-.*: c0 b4 00 00 00 00 [ ]*jgnl de <foo\+0xde>
-.*: c0 b4 00 00 00 00 [ ]*jgnl e4 <foo\+0xe4>
-.*: c0 c4 00 00 00 00 [ ]*jgle ea <foo\+0xea>
-.*: c0 d4 00 00 00 00 [ ]*jgnh f0 <foo\+0xf0>
-.*: c0 d4 00 00 00 00 [ ]*jgnh f6 <foo\+0xf6>
-.*: c0 e4 00 00 00 00 [ ]*jgno fc <foo\+0xfc>
-.*: c0 f4 00 00 00 00 [ ]*jg 102 <foo\+0x102>
-.*: c0 65 00 00 00 00 [ ]*brasl %r6,108 <foo\+0x108>
-.*: c0 65 00 00 00 00 [ ]*brasl %r6,10e <foo\+0x10e>
-.*: c0 65 80 00 00 00 [ ]*brasl %r6,114 <foo\+0x114>
-.*: c0 65 80 00 00 00 [ ]*brasl %r6,11a <foo\+0x11a>
+ *([\da-f]+): c0 04 00 00 00 00 [ ]*jgnop \1 <foo\+0x\1>
+ *([\da-f]+): c0 14 00 00 00 00 [ ]*jgo \1 <foo\+0x\1>
+ *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 <foo\+0x\1>
+ *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 <foo\+0x\1>
+ *([\da-f]+): c0 34 00 00 00 00 [ ]*jgnle \1 <foo\+0x\1>
+ *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 <foo\+0x\1>
+ *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 <foo\+0x\1>
+ *([\da-f]+): c0 54 00 00 00 00 [ ]*jgnhe \1 <foo\+0x\1>
+ *([\da-f]+): c0 64 00 00 00 00 [ ]*jglh \1 <foo\+0x\1>
+ *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 <foo\+0x\1>
+ *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 <foo\+0x\1>
+ *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 <foo\+0x\1>
+ *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 <foo\+0x\1>
+ *([\da-f]+): c0 94 00 00 00 00 [ ]*jgnlh \1 <foo\+0x\1>
+ *([\da-f]+): c0 a4 00 00 00 00 [ ]*jghe \1 <foo\+0x\1>
+ *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 <foo\+0x\1>
+ *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 <foo\+0x\1>
+ *([\da-f]+): c0 c4 00 00 00 00 [ ]*jgle \1 <foo\+0x\1>
+ *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 <foo\+0x\1>
+ *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 <foo\+0x\1>
+ *([\da-f]+): c0 e4 00 00 00 00 [ ]*jgno \1 <foo\+0x\1>
+ *([\da-f]+): c0 f4 00 00 00 00 [ ]*jg \1 <foo\+0x\1>
+ *([\da-f]+): c0 14 00 00 00 00 [ ]*jgo \1 <foo\+0x\1>
+ *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 <foo\+0x\1>
+ *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 <foo\+0x\1>
+ *([\da-f]+): c0 34 00 00 00 00 [ ]*jgnle \1 <foo\+0x\1>
+ *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 <foo\+0x\1>
+ *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 <foo\+0x\1>
+ *([\da-f]+): c0 54 00 00 00 00 [ ]*jgnhe \1 <foo\+0x\1>
+ *([\da-f]+): c0 64 00 00 00 00 [ ]*jglh \1 <foo\+0x\1>
+ *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 <foo\+0x\1>
+ *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 <foo\+0x\1>
+ *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 <foo\+0x\1>
+ *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 <foo\+0x\1>
+ *([\da-f]+): c0 94 00 00 00 00 [ ]*jgnlh \1 <foo\+0x\1>
+ *([\da-f]+): c0 a4 00 00 00 00 [ ]*jghe \1 <foo\+0x\1>
+ *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 <foo\+0x\1>
+ *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 <foo\+0x\1>
+ *([\da-f]+): c0 c4 00 00 00 00 [ ]*jgle \1 <foo\+0x\1>
+ *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 <foo\+0x\1>
+ *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 <foo\+0x\1>
+ *([\da-f]+): c0 e4 00 00 00 00 [ ]*jgno \1 <foo\+0x\1>
+ *([\da-f]+): c0 f4 00 00 00 00 [ ]*jg \1 <foo\+0x\1>
+ *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
.*: c0 65 7f ff ff ff [ ]*brasl %r6,11e <foo\+0x11e>
.*: c0 65 7f ff ff ff [ ]*brasl %r6,124 <foo\+0x124>
.*: 01 0b [ ]*tam
@@ -66,7 +66,7 @@ Disassembly of section .text:
.*: b9 97 00 69 [ ]*dlr %r6,%r9
.*: b9 98 00 69 [ ]*alcr %r6,%r9
.*: b9 99 00 69 [ ]*slbr %r6,%r9
-.*: c0 60 00 00 00 00 [ ]*larl %r6,14e <foo\+0x14e>
+ *([\da-f]+): c0 60 00 00 00 00 [ ]*larl %r6,\1 <foo\+0x\1>
.*: e3 65 af ff 00 1e [ ]*lrv %r6,4095\(%r5,%r10\)
.*: e3 65 af ff 00 1f [ ]*lrvh %r6,4095\(%r5,%r10\)
.*: e3 65 af ff 00 3e [ ]*strv %r6,4095\(%r5,%r10\)
diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
index 183e98ee741..2c7c485a1a1 100644
--- a/gas/testsuite/gas/s390/zarch-z10.d
+++ b/gas/testsuite/gas/s390/zarch-z10.d
@@ -10,9 +10,9 @@ Disassembly of section .text:
.*: eb d6 65 b3 01 7a [ ]*agsi 5555\(%r6\),-42
.*: eb d6 65 b3 01 6e [ ]*alsi 5555\(%r6\),-42
.*: eb d6 65 b3 01 7e [ ]*algsi 5555\(%r6\),-42
-.*: c6 6d 00 00 00 00 [ ]*crl %r6,18 <foo\+0x18>
-.*: c6 68 00 00 00 00 [ ]*cgrl %r6,1e <foo\+0x1e>
-.*: c6 6c 00 00 00 00 [ ]*cgfrl %r6,24 <foo\+0x24>
+ *([\da-f]+): c6 6d 00 00 00 00 [ ]*crl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 68 00 00 00 00 [ ]*cgrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 6c 00 00 00 00 [ ]*cgfrl %r6,\1 <foo\+0x\1>
.*: ec 67 84 57 a0 f6 [ ]*crbnl %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 20 f6 [ ]*crbh %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 20 f6 [ ]*crbh %r6,%r7,1111\(%r8\)
@@ -39,32 +39,32 @@ Disassembly of section .text:
.*: ec 67 84 57 a0 e4 [ ]*cgrbnl %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 c0 e4 [ ]*cgrbnh %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 c0 e4 [ ]*cgrbnh %r6,%r7,1111\(%r8\)
-.*: ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,c6 <foo\+0xc6>
-.*: ec 67 00 00 20 76 [ ]*crjh %r6,%r7,cc <foo\+0xcc>
-.*: ec 67 00 00 20 76 [ ]*crjh %r6,%r7,d2 <foo\+0xd2>
-.*: ec 67 00 00 40 76 [ ]*crjl %r6,%r7,d8 <foo\+0xd8>
-.*: ec 67 00 00 40 76 [ ]*crjl %r6,%r7,de <foo\+0xde>
-.*: ec 67 00 00 60 76 [ ]*crjne %r6,%r7,e4 <foo\+0xe4>
-.*: ec 67 00 00 60 76 [ ]*crjne %r6,%r7,ea <foo\+0xea>
-.*: ec 67 00 00 80 76 [ ]*crje %r6,%r7,f0 <foo\+0xf0>
-.*: ec 67 00 00 80 76 [ ]*crje %r6,%r7,f6 <foo\+0xf6>
-.*: ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,fc <foo\+0xfc>
-.*: ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,102 <foo\+0x102>
-.*: ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,108 <foo\+0x108>
-.*: ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,10e <foo\+0x10e>
-.*: ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,114 <foo\+0x114>
-.*: ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,11a <foo\+0x11a>
-.*: ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,120 <foo\+0x120>
-.*: ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,126 <foo\+0x126>
-.*: ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,12c <foo\+0x12c>
-.*: ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,132 <foo\+0x132>
-.*: ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,138 <foo\+0x138>
-.*: ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,13e <foo\+0x13e>
-.*: ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,144 <foo\+0x144>
-.*: ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,14a <foo\+0x14a>
-.*: ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,150 <foo\+0x150>
-.*: ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,156 <foo\+0x156>
-.*: ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,15c <foo\+0x15c>
+ *([\da-f]+): ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 76 [ ]*crjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 76 [ ]*crjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 76 [ ]*crjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 76 [ ]*crjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 76 [ ]*crjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 76 [ ]*crjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 76 [ ]*crje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 76 [ ]*crje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,\1 <foo\+0x\1>
.*: ec 6a 74 57 d6 fe [ ]*cibnl %r6,-42,1111\(%r7\)
.*: ec 62 74 57 d6 fe [ ]*cibh %r6,-42,1111\(%r7\)
.*: ec 62 74 57 d6 fe [ ]*cibh %r6,-42,1111\(%r7\)
@@ -91,32 +91,32 @@ Disassembly of section .text:
.*: ec 6a 74 57 d6 fc [ ]*cgibnl %r6,-42,1111\(%r7\)
.*: ec 6c 74 57 d6 fc [ ]*cgibnh %r6,-42,1111\(%r7\)
.*: ec 6c 74 57 d6 fc [ ]*cgibnh %r6,-42,1111\(%r7\)
-.*: ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,1fe <foo\+0x1fe>
-.*: ec 62 00 00 d6 7e [ ]*cijh %r6,-42,204 <foo\+0x204>
-.*: ec 62 00 00 d6 7e [ ]*cijh %r6,-42,20a <foo\+0x20a>
-.*: ec 64 00 00 d6 7e [ ]*cijl %r6,-42,210 <foo\+0x210>
-.*: ec 64 00 00 d6 7e [ ]*cijl %r6,-42,216 <foo\+0x216>
-.*: ec 66 00 00 d6 7e [ ]*cijne %r6,-42,21c <foo\+0x21c>
-.*: ec 66 00 00 d6 7e [ ]*cijne %r6,-42,222 <foo\+0x222>
-.*: ec 68 00 00 d6 7e [ ]*cije %r6,-42,228 <foo\+0x228>
-.*: ec 68 00 00 d6 7e [ ]*cije %r6,-42,22e <foo\+0x22e>
-.*: ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,234 <foo\+0x234>
-.*: ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,23a <foo\+0x23a>
-.*: ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,240 <foo\+0x240>
-.*: ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,246 <foo\+0x246>
-.*: ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,24c <foo\+0x24c>
-.*: ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,252 <foo\+0x252>
-.*: ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,258 <foo\+0x258>
-.*: ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,25e <foo\+0x25e>
-.*: ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,264 <foo\+0x264>
-.*: ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,26a <foo\+0x26a>
-.*: ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,270 <foo\+0x270>
-.*: ec 68 00 00 d6 7c [ ]*cgije %r6,-42,276 <foo\+0x276>
-.*: ec 68 00 00 d6 7c [ ]*cgije %r6,-42,27c <foo\+0x27c>
-.*: ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,282 <foo\+0x282>
-.*: ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,288 <foo\+0x288>
-.*: ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,28e <foo\+0x28e>
-.*: ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,294 <foo\+0x294>
+ *([\da-f]+): ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 d6 7e [ ]*cijh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 d6 7e [ ]*cijh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 d6 7e [ ]*cijl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 d6 7e [ ]*cijl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 d6 7e [ ]*cijne %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 d6 7e [ ]*cijne %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 d6 7e [ ]*cije %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 d6 7e [ ]*cije %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 d6 7c [ ]*cgije %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 d6 7c [ ]*cgije %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,\1 <foo\+0x\1>
.*: b9 72 a0 67 [ ]*crtnl %r6,%r7
.*: b9 72 20 67 [ ]*crth %r6,%r7
.*: b9 72 20 67 [ ]*crth %r6,%r7
@@ -173,16 +173,16 @@ Disassembly of section .text:
.*: e5 54 64 57 8a d0 [ ]*chhsi 1111\(%r6\),-30000
.*: e5 5c 64 57 8a d0 [ ]*chsi 1111\(%r6\),-30000
.*: e5 58 64 57 8a d0 [ ]*cghsi 1111\(%r6\),-30000
-.*: c6 65 00 00 00 00 [ ]*chrl %r6,3b6 <foo\+0x3b6>
-.*: c6 64 00 00 00 00 [ ]*cghrl %r6,3bc <foo\+0x3bc>
+ *([\da-f]+): c6 65 00 00 00 00 [ ]*chrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 64 00 00 00 00 [ ]*cghrl %r6,\1 <foo\+0x\1>
.*: e5 55 64 57 9c 40 [ ]*clhhsi 1111\(%r6\),40000
.*: e5 5d 64 57 9c 40 [ ]*clfhsi 1111\(%r6\),40000
.*: e5 59 64 57 9c 40 [ ]*clghsi 1111\(%r6\),40000
-.*: c6 6f 00 00 00 00 [ ]*clrl %r6,3d4 <foo\+0x3d4>
-.*: c6 6a 00 00 00 00 [ ]*clgrl %r6,3da <foo\+0x3da>
-.*: c6 6e 00 00 00 00 [ ]*clgfrl %r6,3e0 <foo\+0x3e0>
-.*: c6 67 00 00 00 00 [ ]*clhrl %r6,3e6 <foo\+0x3e6>
-.*: c6 66 00 00 00 00 [ ]*clghrl %r6,3ec <foo\+0x3ec>
+ *([\da-f]+): c6 6f 00 00 00 00 [ ]*clrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 6a 00 00 00 00 [ ]*clgrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 6e 00 00 00 00 [ ]*clgfrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 67 00 00 00 00 [ ]*clhrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 66 00 00 00 00 [ ]*clghrl %r6,\1 <foo\+0x\1>
.*: ec 67 84 57 a0 f7 [ ]*clrbnl %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 20 f7 [ ]*clrbh %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 20 f7 [ ]*clrbh %r6,%r7,1111\(%r8\)
@@ -209,32 +209,32 @@ Disassembly of section .text:
.*: ec 67 84 57 a0 e5 [ ]*clgrbnl %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 c0 e5 [ ]*clgrbnh %r6,%r7,1111\(%r8\)
.*: ec 67 84 57 c0 e5 [ ]*clgrbnh %r6,%r7,1111\(%r8\)
-.*: ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,48e <foo\+0x48e>
-.*: ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,494 <foo\+0x494>
-.*: ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,49a <foo\+0x49a>
-.*: ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,4a0 <foo\+0x4a0>
-.*: ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,4a6 <foo\+0x4a6>
-.*: ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,4ac <foo\+0x4ac>
-.*: ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,4b2 <foo\+0x4b2>
-.*: ec 67 00 00 80 77 [ ]*clrje %r6,%r7,4b8 <foo\+0x4b8>
-.*: ec 67 00 00 80 77 [ ]*clrje %r6,%r7,4be <foo\+0x4be>
-.*: ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,4c4 <foo\+0x4c4>
-.*: ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,4ca <foo\+0x4ca>
-.*: ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,4d0 <foo\+0x4d0>
-.*: ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,4d6 <foo\+0x4d6>
-.*: ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,4dc <foo\+0x4dc>
-.*: ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,4e2 <foo\+0x4e2>
-.*: ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,4e8 <foo\+0x4e8>
-.*: ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,4ee <foo\+0x4ee>
-.*: ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,4f4 <foo\+0x4f4>
-.*: ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,4fa <foo\+0x4fa>
-.*: ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,500 <foo\+0x500>
-.*: ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,506 <foo\+0x506>
-.*: ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,50c <foo\+0x50c>
-.*: ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,512 <foo\+0x512>
-.*: ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,518 <foo\+0x518>
-.*: ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,51e <foo\+0x51e>
-.*: ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,524 <foo\+0x524>
+ *([\da-f]+): ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 77 [ ]*clrje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 77 [ ]*clrje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,\1 <foo\+0x\1>
+ *([\da-f]+): ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,\1 <foo\+0x\1>
.*: ec 6a 74 57 c8 ff [ ]*clibnl %r6,200,1111\(%r7\)
.*: ec 62 74 57 c8 ff [ ]*clibh %r6,200,1111\(%r7\)
.*: ec 62 74 57 c8 ff [ ]*clibh %r6,200,1111\(%r7\)
@@ -261,32 +261,32 @@ Disassembly of section .text:
.*: ec 6a 74 57 c8 fd [ ]*clgibnl %r6,200,1111\(%r7\)
.*: ec 6c 74 57 c8 fd [ ]*clgibnh %r6,200,1111\(%r7\)
.*: ec 6c 74 57 c8 fd [ ]*clgibnh %r6,200,1111\(%r7\)
-.*: ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,5c6 <foo\+0x5c6>
-.*: ec 62 00 00 c8 7f [ ]*clijh %r6,200,5cc <foo\+0x5cc>
-.*: ec 62 00 00 c8 7f [ ]*clijh %r6,200,5d2 <foo\+0x5d2>
-.*: ec 64 00 00 c8 7f [ ]*clijl %r6,200,5d8 <foo\+0x5d8>
-.*: ec 64 00 00 c8 7f [ ]*clijl %r6,200,5de <foo\+0x5de>
-.*: ec 66 00 00 c8 7f [ ]*clijne %r6,200,5e4 <foo\+0x5e4>
-.*: ec 66 00 00 c8 7f [ ]*clijne %r6,200,5ea <foo\+0x5ea>
-.*: ec 68 00 00 c8 7f [ ]*clije %r6,200,5f0 <foo\+0x5f0>
-.*: ec 68 00 00 c8 7f [ ]*clije %r6,200,5f6 <foo\+0x5f6>
-.*: ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,5fc <foo\+0x5fc>
-.*: ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,602 <foo\+0x602>
-.*: ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,608 <foo\+0x608>
-.*: ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,60e <foo\+0x60e>
-.*: ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,614 <foo\+0x614>
-.*: ec 62 00 00 c8 7d [ ]*clgijh %r6,200,61a <foo\+0x61a>
-.*: ec 62 00 00 c8 7d [ ]*clgijh %r6,200,620 <foo\+0x620>
-.*: ec 64 00 00 c8 7d [ ]*clgijl %r6,200,626 <foo\+0x626>
-.*: ec 64 00 00 c8 7d [ ]*clgijl %r6,200,62c <foo\+0x62c>
-.*: ec 66 00 00 c8 7d [ ]*clgijne %r6,200,632 <foo\+0x632>
-.*: ec 66 00 00 c8 7d [ ]*clgijne %r6,200,638 <foo\+0x638>
-.*: ec 68 00 00 c8 7d [ ]*clgije %r6,200,63e <foo\+0x63e>
-.*: ec 68 00 00 c8 7d [ ]*clgije %r6,200,644 <foo\+0x644>
-.*: ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,64a <foo\+0x64a>
-.*: ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,650 <foo\+0x650>
-.*: ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,656 <foo\+0x656>
-.*: ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,65c <foo\+0x65c>
+ *([\da-f]+): ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 c8 7f [ ]*clijh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 c8 7f [ ]*clijh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 c8 7f [ ]*clijl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 c8 7f [ ]*clijl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 c8 7f [ ]*clijne %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 c8 7f [ ]*clijne %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 c8 7f [ ]*clije %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 c8 7f [ ]*clije %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 c8 7d [ ]*clgijh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 62 00 00 c8 7d [ ]*clgijh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 c8 7d [ ]*clgijl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 64 00 00 c8 7d [ ]*clgijl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 c8 7d [ ]*clgijne %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 66 00 00 c8 7d [ ]*clgijne %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 c8 7d [ ]*clgije %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 68 00 00 c8 7d [ ]*clgije %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,\1 <foo\+0x\1>
+ *([\da-f]+): ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,\1 <foo\+0x\1>
.*: b9 73 a0 67 [ ]*clrtnl %r6,%r7
.*: b9 73 20 67 [ ]*clrth %r6,%r7
.*: b9 73 20 67 [ ]*clrth %r6,%r7
@@ -340,16 +340,16 @@ Disassembly of section .text:
.*: ec 60 75 30 c0 71 [ ]*clgitnh %r6,30000
.*: ec 60 75 30 c0 71 [ ]*clgitnh %r6,30000
.*: eb 67 84 57 00 4c [ ]*ecag %r6,%r7,1111\(%r8\)
-.*: c4 6d 00 00 00 00 [ ]*lrl %r6,76c <foo\+0x76c>
-.*: c4 68 00 00 00 00 [ ]*lgrl %r6,772 <foo\+0x772>
-.*: c4 6c 00 00 00 00 [ ]*lgfrl %r6,778 <foo\+0x778>
+ *([\da-f]+): c4 6d 00 00 00 00 [ ]*lrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 68 00 00 00 00 [ ]*lgrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 6c 00 00 00 00 [ ]*lgfrl %r6,\1 <foo\+0x\1>
.*: e3 67 85 b3 01 75 [ ]*laey %r6,5555\(%r7,%r8\)
.*: e3 67 85 b3 01 32 [ ]*ltgf %r6,5555\(%r7,%r8\)
-.*: c4 65 00 00 00 00 [ ]*lhrl %r6,78a <foo\+0x78a>
-.*: c4 64 00 00 00 00 [ ]*lghrl %r6,790 <foo\+0x790>
-.*: c4 6e 00 00 00 00 [ ]*llgfrl %r6,796 <foo\+0x796>
-.*: c4 62 00 00 00 00 [ ]*llhrl %r6,79c <foo\+0x79c>
-.*: c4 66 00 00 00 00 [ ]*llghrl %r6,7a2 <foo\+0x7a2>
+ *([\da-f]+): c4 65 00 00 00 00 [ ]*lhrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 64 00 00 00 00 [ ]*lghrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 6e 00 00 00 00 [ ]*llgfrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 62 00 00 00 00 [ ]*llhrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 66 00 00 00 00 [ ]*llghrl %r6,\1 <foo\+0x\1>
.*: e5 44 64 57 8a d0 [ ]*mvhhi 1111\(%r6\),-30000
.*: e5 4c 64 57 8a d0 [ ]*mvhi 1111\(%r6\),-30000
.*: e5 48 64 57 8a d0 [ ]*mvghi 1111\(%r6\),-30000
@@ -358,17 +358,17 @@ Disassembly of section .text:
.*: c2 61 ff fe 79 60 [ ]*msfi %r6,-100000
.*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000
.*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
-.*: c6 a2 00 00 00 00 [ ]*pfdrl 10,7d8 <foo\+0x7d8>
+ *([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
.*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230
.*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230
.*: ec 67 d2 94 e6 55 [ ]*risbgz %r6,%r7,210,20,230
-.*: c4 6f 00 00 00 00 [ ]*strl %r6,802 <foo\+0x802>
-.*: c4 6b 00 00 00 00 [ ]*stgrl %r6,808 <foo\+0x808>
-.*: c4 67 00 00 00 00 [ ]*sthrl %r6,80e <foo\+0x80e>
-.*: c6 60 00 00 00 00 [ ]*exrl %r6,814 <foo\+0x814>
+ *([\da-f]+): c4 6f 00 00 00 00 [ ]*strl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 6b 00 00 00 00 [ ]*stgrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c4 67 00 00 00 00 [ ]*sthrl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c6 60 00 00 00 00 [ ]*exrl %r6,\1 <foo\+0x\1>
.*: af ee 6d 05 [ ]*mc 3333\(%r6\),238
.*: b9 a2 00 60 [ ]*ptf %r6
.*: b9 af 00 67 [ ]*pfmf %r6,%r7
diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d
index 3889d32e02f..0f8bfeafa25 100644
--- a/gas/testsuite/gas/s390/zarch-z196.d
+++ b/gas/testsuite/gas/s390/zarch-z196.d
@@ -13,7 +13,7 @@ Disassembly of section .text:
.*: b9 da 80 67 [ ]*alhhlr %r6,%r7,%r8
.*: cc 6a 00 00 fd e8 [ ]*alsih %r6,65000
.*: cc 6b 00 00 fd e8 [ ]*alsihn %r6,65000
-.*: cc 66 00 00 00 00 [ ]*brcth %r6,22 <foo\+0x22>
+ *([\da-f]+): cc 66 00 00 00 00 [ ]*brcth %r6,\1 <foo\+0x\1>
.*: b9 cd 00 67 [ ]*chhr %r6,%r7
.*: b9 dd 00 67 [ ]*chlr %r6,%r7
.*: e3 67 85 b3 01 cd [ ]*chf %r6,5555\(%r7,%r8\)
diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d
index 8d292dfc11b..2848dc1eb7c 100644
--- a/gas/testsuite/gas/s390/zarch-z900.d
+++ b/gas/testsuite/gas/s390/zarch-z900.d
@@ -19,12 +19,12 @@ Disassembly of section .text:
.*: b9 0a 00 96 [ ]*algr %r9,%r6
.*: e3 95 af ff 00 46 [ ]*bctg %r9,4095\(%r5,%r10\)
.*: b9 46 00 96 [ ]*bctgr %r9,%r6
-.*: a7 97 00 00 [ ]*brctg %r9,40 \<foo\+0x40\>
-.*: a7 67 00 00 [ ]*brctg %r6,44 <foo\+0x44>
-.*: ec 96 00 00 00 44 [ ]*brxhg %r9,%r6,48 <foo\+0x48>
-.*: ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,4e <foo\+0x4e>
-.*: ec 96 00 00 00 45 [ ]*brxlg %r9,%r6,54 <foo\+0x54>
-.*: ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,5a <foo\+0x5a>
+ *([\da-f]+): a7 97 00 00 [ ]*brctg %r9,\1 <foo\+0x\1>
+ *([\da-f]+): a7 67 00 00 [ ]*brctg %r6,\1 <foo\+0x\1>
+ *([\da-f]+): ec 96 00 00 00 44 [ ]*brxhg %r9,%r6,\1 <foo\+0x\1>
+ *([\da-f]+): ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,\1 <foo\+0x\1>
+ *([\da-f]+): ec 96 00 00 00 45 [ ]*brxlg %r9,%r6,\1 <foo\+0x\1>
+ *([\da-f]+): ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,\1 <foo\+0x\1>
.*: eb 96 5f ff 00 44 [ ]*bxhg %r9,%r6,4095\(%r5\)
.*: eb 96 5f ff 00 45 [ ]*bxleg %r9,%r6,4095\(%r5\)
.*: b3 a5 00 96 [ ]*cdgbr %f9,%r6
diff --git a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d
index e25ac134e1f..96bf59b9fb0 100644
--- a/gas/testsuite/gas/s390/zarch-zEC12.d
+++ b/gas/testsuite/gas/s390/zarch-zEC12.d
@@ -57,12 +57,12 @@ Disassembly of section .text:
.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9
.*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1
.*: c5 a0 0c 00 00 0c [ ]*bprp 10,136 <bar>,136 <bar>
-.*: c5 a0 00 00 00 00 [ ]*bprp 10,124 <foo\+0x124>,124 <foo\+0x124>
+ *([\da-f]+): c5 a0 00 00 00 00 [ ]*bprp 10,\1 <foo\+0x\1>,\1 <foo\+0x\1>
[ ]*125: R_390_PLT12DBL bar\+0x1
[ ]*127: R_390_PLT24DBL bar\+0x3
-.*: c7 a0 00 00 00 00 [ ]*bpp 10,12a <foo\+0x12a>,0
+ *([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 <foo\+0x\1>,0
[ ]*12e: R_390_PLT16DBL bar\+0x4
-.*: c7 a0 00 00 00 00 [ ]*bpp 10,130 <foo\+0x130>,0
+ *([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 <foo\+0x\1>,0
[ ]*134: R_390_PC16DBL baz\+0x4
--
2.47.0

63
SOURCES/binutils-s390-arch15-part-02.patch
Unescape View File

@ -0,0 +1,63 @@
From 3f3c1e513bdf53d78adbde7f9d300c2281de21b9 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 23 Nov 2023 15:44:41 +0100
Subject: [PATCH] s390: Add brasl edge test cases from ESA to z/Architecture
Commit: 8f44c72d1f4f
The ESA opcode test cases for IBM z900 contain a few edge cases. They
exercise the brasl mnemonic with its largest allowed negative and
positive offsets. Linux on zSeries in ESA mode executes in 31-bit
addressing mode. Therefore the ESA test cases are assembled with -m31.
In 31-bit addressing mode the address computation using those large
offsets wraps, which is correctly reflected in the disassembly.
Linux on Z in z/Architecture mode executes in 64-bit addressing mode.
Therefore the z/Architecture (zarch) test cases are assembled with -m64.
In 64-bit addressing mode the address computation using those large
offsets does not necessarily wrap.
gas/
* testsuite/gas/s390/zarch-z900.s: Add brasl tests from ESA that
exercise edge cases.
* testsuite/gas/s390/zarch-z900.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
gas/testsuite/gas/s390/zarch-z900.d | 6 ++++++
gas/testsuite/gas/s390/zarch-z900.s | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d
index 2848dc1eb7c..93aee212785 100644
--- a/gas/testsuite/gas/s390/zarch-z900.d
+++ b/gas/testsuite/gas/s390/zarch-z900.d
@@ -149,4 +149,10 @@ Disassembly of section .text:
.*: eb 96 5f ff 00 0f [ ]*tracg %r9,%r6,4095\(%r5\)
.*: e3 95 af ff 00 82 [ ]*xg %r9,4095\(%r5,%r10\)
.*: b9 82 00 96 [ ]*xgr %r9,%r6
+ *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
+ *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 <foo\+0xffffffff0+\1>
+ *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 <foo\+0xffffffff0+\1>
+.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d0 <foo\+0x1000002d0>
+.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d6 <foo\+0x1000002d6>
.*: 07 07 [ ]*nopr %r7
diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s
index 96d27e7b7e2..22fa1da5a30 100644
--- a/gas/testsuite/gas/s390/zarch-z900.s
+++ b/gas/testsuite/gas/s390/zarch-z900.s
@@ -143,3 +143,9 @@ foo:
tracg %r9,%r6,4095(%r5)
xg %r9,4095(%r5,%r10)
xgr %r9,%r6
+ brasl %r6,.
+ jasl %r6,.
+ brasl %r6,.-0x100000000
+ jasl %r6,.-0x100000000
+ brasl %r6,.+0xfffffffe
+ jasl %r6,.+0xfffffffe
--
2.47.0

349
SOURCES/binutils-s390-arch15-part-03.patch
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@ -0,0 +1,349 @@
From eeafc61979c6f8399bb5ce770e46a00823a5cfae Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 23 Nov 2023 15:45:42 +0100
Subject: [PATCH] s390: Make operand table indices relative to each other
Commit: 002dddf0b965
This is a purely mechanical change. It allows subsequent insertions into
the operands table without having to renumber all operand indices.
The only differences in the resulting ELF object are in the .debug_info
section. This has been confirmed by diffing the following xxd and readelf
output:
xxd s390-opc.o
readelf -aW -x .text -x .data -x .bss -x .rodata -x .debug_info \
-x .symtab -x .strtab -x .shstrtab --debug-dump s390-opc.o
opcodes/
* s390-opc.c: Make operand table indices relative to each other.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
opcodes/s390-opc.c | 174 ++++++++++++++++++++++++---------------------
1 file changed, 92 insertions(+), 82 deletions(-)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 1910431ab89..b52fc8c3b62 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -34,76 +34,82 @@
inserting operands into instructions and vice-versa is kept in this
file. */
+/* Build-time checks are preferrable over runtime ones. Use this construct
+ in preference where possible. */
+#define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); }))
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
/* The operands table.
The fields are bits, shift, insert, extract, flags. */
const struct s390_operand s390_operands[] =
{
-#define UNUSED 0
+#define UNUSED 0
{ 0, 0, 0 }, /* Indicates the end of the operand list */
/* General purpose register operands. */
-#define R_8 1 /* GPR starting at position 8 */
+#define R_8 (UNUSED + 1) /* GPR starting at position 8 */
{ 4, 8, S390_OPERAND_GPR },
-#define R_12 2 /* GPR starting at position 12 */
+#define R_12 (R_8 + 1) /* GPR starting at position 12 */
{ 4, 12, S390_OPERAND_GPR },
-#define R_16 3 /* GPR starting at position 16 */
+#define R_16 (R_12 + 1) /* GPR starting at position 16 */
{ 4, 16, S390_OPERAND_GPR },
-#define R_20 4 /* GPR starting at position 20 */
+#define R_20 (R_16 + 1) /* GPR starting at position 20 */
{ 4, 20, S390_OPERAND_GPR },
-#define R_24 5 /* GPR starting at position 24 */
+#define R_24 (R_20 + 1) /* GPR starting at position 24 */
{ 4, 24, S390_OPERAND_GPR },
-#define R_28 6 /* GPR starting at position 28 */
+#define R_28 (R_24 + 1) /* GPR starting at position 28 */
{ 4, 28, S390_OPERAND_GPR },
-#define R_32 7 /* GPR starting at position 32 */
+#define R_32 (R_28 + 1) /* GPR starting at position 32 */
{ 4, 32, S390_OPERAND_GPR },
/* General purpose register pair operands. */
-#define RE_8 8 /* GPR starting at position 8 */
+#define RE_8 (R_32 + 1) /* GPR starting at position 8 */
{ 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
-#define RE_12 9 /* GPR starting at position 12 */
+#define RE_12 (RE_8 + 1) /* GPR starting at position 12 */
{ 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
-#define RE_16 10 /* GPR starting at position 16 */
+#define RE_16 (RE_12 + 1) /* GPR starting at position 16 */
{ 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
-#define RE_20 11 /* GPR starting at position 20 */
+#define RE_20 (RE_16 + 1) /* GPR starting at position 20 */
{ 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
-#define RE_24 12 /* GPR starting at position 24 */
+#define RE_24 (RE_20 + 1) /* GPR starting at position 24 */
{ 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
-#define RE_28 13 /* GPR starting at position 28 */
+#define RE_28 (RE_24 + 1) /* GPR starting at position 28 */
{ 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
-#define RE_32 14 /* GPR starting at position 32 */
+#define RE_32 (RE_28 + 1) /* GPR starting at position 32 */
{ 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
/* Floating point register operands. */
-#define F_8 15 /* FPR starting at position 8 */
+#define F_8 (RE_32 + 1) /* FPR starting at position 8 */
{ 4, 8, S390_OPERAND_FPR },
-#define F_12 16 /* FPR starting at position 12 */
+#define F_12 (F_8 + 1) /* FPR starting at position 12 */
{ 4, 12, S390_OPERAND_FPR },
-#define F_16 17 /* FPR starting at position 16 */
+#define F_16 (F_12 + 1) /* FPR starting at position 16 */
{ 4, 16, S390_OPERAND_FPR },
-#define F_24 18 /* FPR starting at position 24 */
+#define F_24 (F_16 + 1) /* FPR starting at position 24 */
{ 4, 24, S390_OPERAND_FPR },
-#define F_28 19 /* FPR starting at position 28 */
+#define F_28 (F_24 + 1) /* FPR starting at position 28 */
{ 4, 28, S390_OPERAND_FPR },
-#define F_32 20 /* FPR starting at position 32 */
+#define F_32 (F_28 + 1) /* FPR starting at position 32 */
{ 4, 32, S390_OPERAND_FPR },
/* Floating point register pair operands. */
-#define FE_8 21 /* FPR starting at position 8 */
+#define FE_8 (F_32 + 1) /* FPR starting at position 8 */
{ 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
-#define FE_12 22 /* FPR starting at position 12 */
+#define FE_12 (FE_8 + 1) /* FPR starting at position 12 */
{ 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
-#define FE_16 23 /* FPR starting at position 16 */
+#define FE_16 (FE_12 + 1) /* FPR starting at position 16 */
{ 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
-#define FE_24 24 /* FPR starting at position 24 */
+#define FE_24 (FE_16 + 1) /* FPR starting at position 24 */
{ 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
-#define FE_28 25 /* FPR starting at position 28 */
+#define FE_28 (FE_24 + 1) /* FPR starting at position 28 */
{ 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
-#define FE_32 26 /* FPR starting at position 32 */
+#define FE_32 (FE_28 + 1) /* FPR starting at position 32 */
{ 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
/* Vector register operands. */
@@ -111,145 +117,149 @@ const struct s390_operand s390_operands[] =
/* For each of these operands and additional bit in the RXB operand is
needed. */
-#define V_8 27 /* Vector reg. starting at position 8 */
+#define V_8 (FE_32 + 1) /* Vector reg. starting at position 8 */
{ 4, 8, S390_OPERAND_VR },
-#define V_12 28 /* Vector reg. starting at position 12 */
+#define V_12 (V_8 + 1) /* Vector reg. starting at position 12 */
{ 4, 12, S390_OPERAND_VR },
-#define V_CP16_12 29 /* Vector reg. starting at position 12 */
+#define V_CP16_12 (V_12 + 1) /* Vector reg. starting at position 12 */
{ 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */
-#define V_16 30 /* Vector reg. starting at position 16 */
+#define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */
{ 4, 16, S390_OPERAND_VR },
-#define V_32 31 /* Vector reg. starting at position 32 */
+#define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */
{ 4, 32, S390_OPERAND_VR },
/* Access register operands. */
-#define A_8 32 /* Access reg. starting at position 8 */
+#define A_8 (V_32 + 1) /* Access reg. starting at position 8 */
{ 4, 8, S390_OPERAND_AR },
-#define A_12 33 /* Access reg. starting at position 12 */
+#define A_12 (A_8 + 1) /* Access reg. starting at position 12 */
{ 4, 12, S390_OPERAND_AR },
-#define A_24 34 /* Access reg. starting at position 24 */
+#define A_24 (A_12 + 1) /* Access reg. starting at position 24 */
{ 4, 24, S390_OPERAND_AR },
-#define A_28 35 /* Access reg. starting at position 28 */
+#define A_28 (A_24 + 1) /* Access reg. starting at position 28 */
{ 4, 28, S390_OPERAND_AR },
/* Control register operands. */
-#define C_8 36 /* Control reg. starting at position 8 */
+#define C_8 (A_28 + 1) /* Control reg. starting at position 8 */
{ 4, 8, S390_OPERAND_CR },
-#define C_12 37 /* Control reg. starting at position 12 */
+#define C_12 (C_8 + 1) /* Control reg. starting at position 12 */
{ 4, 12, S390_OPERAND_CR },
/* Base register operands. */
-#define B_16 38 /* Base register starting at position 16 */
+#define B_16 (C_12 + 1) /* Base register starting at position 16 */
{ 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR },
-#define B_32 39 /* Base register starting at position 32 */
+#define B_32 (B_16 + 1) /* Base register starting at position 32 */
{ 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR },
-#define X_12 40 /* Index register starting at position 12 */
+#define X_12 (B_32 + 1) /* Index register starting at position 12 */
{ 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR },
-#define VX_12 41 /* Vector index register starting at position 12 */
+#define VX_12 (X_12+1) /* Vector index register starting at position 12 */
{ 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR },
/* Address displacement operands. */
-#define D_20 42 /* Displacement starting at position 20 */
+#define D_20 (VX_12 + 1) /* Displacement starting at position 20 */
{ 12, 20, S390_OPERAND_DISP },
-#define D_36 43 /* Displacement starting at position 36 */
+#define D_36 (D_20 + 1) /* Displacement starting at position 36 */
{ 12, 36, S390_OPERAND_DISP },
-#define D20_20 44 /* 20 bit displacement starting at 20 */
+#define D20_20 (D_36 + 1) /* 20 bit displacement starting at 20 */
{ 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED },
/* Length operands. */
-#define L4_8 45 /* 4 bit length starting at position 8 */
+#define L4_8 (D20_20 + 1) /* 4 bit length starting at position 8 */
{ 4, 8, S390_OPERAND_LENGTH },
-#define L4_12 46 /* 4 bit length starting at position 12 */
+#define L4_12 (L4_8 + 1) /* 4 bit length starting at position 12 */
{ 4, 12, S390_OPERAND_LENGTH },
-#define L8_8 47 /* 8 bit length starting at position 8 */
+#define L8_8 (L4_12 + 1) /* 8 bit length starting at position 8 */
{ 8, 8, S390_OPERAND_LENGTH },
/* Signed immediate operands. */
-#define I8_8 48 /* 8 bit signed value starting at 8 */
+#define I8_8 (L8_8 + 1) /* 8 bit signed value starting at 8 */
{ 8, 8, S390_OPERAND_SIGNED },
-#define I8_32 49 /* 8 bit signed value starting at 32 */
+#define I8_32 (I8_8 + 1) /* 8 bit signed value starting at 32 */
{ 8, 32, S390_OPERAND_SIGNED },
-#define I12_12 50 /* 12 bit signed value starting at 12 */
+#define I12_12 (I8_32 + 1) /* 12 bit signed value starting at 12 */
{ 12, 12, S390_OPERAND_SIGNED },
-#define I16_16 51 /* 16 bit signed value starting at 16 */
+#define I16_16 (I12_12 + 1) /* 16 bit signed value starting at 16 */
{ 16, 16, S390_OPERAND_SIGNED },
-#define I16_32 52 /* 16 bit signed value starting at 32 */
+#define I16_32 (I16_16 + 1) /* 16 bit signed value starting at 32 */
{ 16, 32, S390_OPERAND_SIGNED },
-#define I24_24 53 /* 24 bit signed value starting at 24 */
+#define I24_24 (I16_32 + 1) /* 24 bit signed value starting at 24 */
{ 24, 24, S390_OPERAND_SIGNED },
-#define I32_16 54 /* 32 bit signed value starting at 16 */
+#define I32_16 (I24_24 + 1) /* 32 bit signed value starting at 16 */
{ 32, 16, S390_OPERAND_SIGNED },
/* Unsigned immediate operands. */
-#define U4_8 55 /* 4 bit unsigned value starting at 8 */
+#define U4_8 (I32_16 + 1) /* 4 bit unsigned value starting at 8 */
{ 4, 8, 0 },
-#define U4_12 56 /* 4 bit unsigned value starting at 12 */
+#define U4_12 (U4_8 + 1) /* 4 bit unsigned value starting at 12 */
{ 4, 12, 0 },
-#define U4_16 57 /* 4 bit unsigned value starting at 16 */
+#define U4_16 (U4_12 + 1) /* 4 bit unsigned value starting at 16 */
{ 4, 16, 0 },
-#define U4_20 58 /* 4 bit unsigned value starting at 20 */
+#define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 */
{ 4, 20, 0 },
-#define U4_24 59 /* 4 bit unsigned value starting at 24 */
+#define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */
{ 4, 24, 0 },
-#define U4_OR1_24 60 /* 4 bit unsigned value ORed with 1 */
+#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */
{ 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */
-#define U4_OR2_24 61 /* 4 bit unsigned value ORed with 2 */
+#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */
{ 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_OR3_24 62 /* 4 bit unsigned value ORed with 3 */
+#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */
{ 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_28 63 /* 4 bit unsigned value starting at 28 */
+#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */
{ 4, 28, 0 },
-#define U4_OR8_28 64 /* 4 bit unsigned value ORed with 8 */
+#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */
{ 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */
-#define U4_32 65 /* 4 bit unsigned value starting at 32 */
+#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */
{ 4, 32, 0 },
-#define U4_36 66 /* 4 bit unsigned value starting at 36 */
+#define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */
{ 4, 36, 0 },
-#define U8_8 67 /* 8 bit unsigned value starting at 8 */
+#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
-#define U8_16 68 /* 8 bit unsigned value starting at 16 */
+#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
-#define U6_26 69 /* 6 bit unsigned value starting at 26 */
+#define U6_26 (U8_16 + 1) /* 6 bit unsigned value starting at 26 */
{ 6, 26, 0 },
-#define U8_24 70 /* 8 bit unsigned value starting at 24 */
+#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
-#define U8_28 71 /* 8 bit unsigned value starting at 28 */
+#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */
{ 8, 28, 0 },
-#define U8_32 72 /* 8 bit unsigned value starting at 32 */
+#define U8_32 (U8_28 + 1) /* 8 bit unsigned value starting at 32 */
{ 8, 32, 0 },
-#define U12_16 73 /* 12 bit unsigned value starting at 16 */
+#define U12_16 (U8_32 + 1) /* 12 bit unsigned value starting at 16 */
{ 12, 16, 0 },
-#define U16_16 74 /* 16 bit unsigned value starting at 16 */
+#define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */
{ 16, 16, 0 },
-#define U16_32 75 /* 16 bit unsigned value starting at 32 */
+#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */
{ 16, 32, 0 },
-#define U32_16 76 /* 32 bit unsigned value starting at 16 */
+#define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */
{ 32, 16, 0 },
/* PC-relative address operands. */
-#define J12_12 77 /* 12 bit PC relative offset at 12 */
+#define J12_12 (U32_16 + 1) /* 12 bit PC relative offset at 12 */
{ 12, 12, S390_OPERAND_PCREL },
-#define J16_16 78 /* 16 bit PC relative offset at 16 */
+#define J16_16 (J12_12 + 1) /* 16 bit PC relative offset at 16 */
{ 16, 16, S390_OPERAND_PCREL },
-#define J16_32 79 /* 16 bit PC relative offset at 32 */
+#define J16_32 (J16_16 + 1) /* 16 bit PC relative offset at 32 */
{ 16, 32, S390_OPERAND_PCREL },
-#define J24_24 80 /* 24 bit PC relative offset at 24 */
+#define J24_24 (J16_32 + 1) /* 24 bit PC relative offset at 24 */
{ 24, 24, S390_OPERAND_PCREL },
-#define J32_16 81 /* 32 bit PC relative offset at 16 */
+#define J32_16 (J24_24 + 1) /* 32 bit PC relative offset at 16 */
{ 32, 16, S390_OPERAND_PCREL },
};
+static inline void unused_s390_operands_static_asserts(void)
+{
+ static_assert(ARRAY_SIZE(s390_operands) - 1 == J32_16);
+}
/* Macros used to form opcodes. */
--
2.47.0

237
SOURCES/binutils-s390-arch15-part-04.patch
Unescape View File

@ -0,0 +1,237 @@
From fca086d928a940dc5aa3b5c0586bc5ed37d6b374 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 23 Nov 2023 15:46:46 +0100
Subject: [PATCH] s390: Align optional operand definition to specs
Commit: 1f53fac2bdd5
The IBM z/Architecture Principle of Operation [1] specifies the last
operand(s) of some (extended) mnemonics to be optional. Align the
mnemonic definitions in the opcode table according to specification.
This changes the last operand of the following (extended) mnemonics to
be optional:
risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg
Note that efpc and sfpc actually have only one operand, but had
erroneously been defined to have two. For backwards compatibility the
wrong RR register format must be retained. Since the superfluous second
operand is defined as optional the instruction can still be coded as
specified.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-opc.txt: Align optional operand definition to
specification.
testsuite/
* zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg,
and rxsbg.
* zarch-z10.d: Likewise.
* zarch-z196.s: Add test cases for risbhg and risblg.
* zarch-z196.d: Likewise.
* zarch-zEC12.s: Add test cases for risbgn and risbgnz.
* zarch-zEC12.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
gas/testsuite/gas/s390/zarch-z10.d | 6 ++++++
gas/testsuite/gas/s390/zarch-z10.s | 6 ++++++
gas/testsuite/gas/s390/zarch-z196.d | 2 ++
gas/testsuite/gas/s390/zarch-z196.s | 2 ++
gas/testsuite/gas/s390/zarch-zEC12.d | 18 ++++++++----------
gas/testsuite/gas/s390/zarch-zEC12.s | 3 +++
opcodes/s390-opc.txt | 20 +++++++++++---------
7 files changed, 38 insertions(+), 19 deletions(-)
diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
index 2c7c485a1a1..4aca8372363 100644
--- a/gas/testsuite/gas/s390/zarch-z10.d
+++ b/gas/testsuite/gas/s390/zarch-z10.d
@@ -360,11 +360,17 @@ Disassembly of section .text:
.*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
*([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
+.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220
.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
+.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220
.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
+.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220
.*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230
+.*: ec 67 d2 14 00 55 [ ]*risbg %r6,%r7,210,20
.*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230
+.*: ec 67 d2 bc 00 55 [ ]*risbgz %r6,%r7,210,60
.*: ec 67 d2 94 e6 55 [ ]*risbgz %r6,%r7,210,20,230
+.*: ec 67 d2 94 00 55 [ ]*risbgz %r6,%r7,210,20
*([\da-f]+): c4 6f 00 00 00 00 [ ]*strl %r6,\1 <foo\+0x\1>
*([\da-f]+): c4 6b 00 00 00 00 [ ]*stgrl %r6,\1 <foo\+0x\1>
*([\da-f]+): c4 67 00 00 00 00 [ ]*sthrl %r6,\1 <foo\+0x\1>
diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s
index 5cfc533d4d1..3ed61a4f0fd 100644
--- a/gas/testsuite/gas/s390/zarch-z10.s
+++ b/gas/testsuite/gas/s390/zarch-z10.s
@@ -354,11 +354,17 @@ foo:
pfd 10,5555(%r6,%r7)
pfdrl 10,.
rnsbg %r6,%r7,210,220,230
+ rnsbg %r6,%r7,210,220
rxsbg %r6,%r7,210,220,230
+ rxsbg %r6,%r7,210,220
rosbg %r6,%r7,210,220,230
+ rosbg %r6,%r7,210,220
risbg %r6,%r7,210,20,230
+ risbg %r6,%r7,210,20
risbg %r6,%r7,210,188,230
+ risbg %r6,%r7,210,188
risbgz %r6,%r7,210,20,230
+ risbgz %r6,%r7,210,20
strl %r6,.
stgrl %r6,.
sthrl %r6,.
diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d
index 0f8bfeafa25..b9db65f43ee 100644
--- a/gas/testsuite/gas/s390/zarch-z196.d
+++ b/gas/testsuite/gas/s390/zarch-z196.d
@@ -29,7 +29,9 @@ Disassembly of section .text:
.*: e3 67 8a 4d fe c2 [ ]*llch %r6,-5555\(%r7,%r8\)
.*: e3 67 8a 4d fe c6 [ ]*llhh %r6,-5555\(%r7,%r8\)
.*: ec 67 0c 0d 0e 5d [ ]*risbhg %r6,%r7,12,13,14
+.*: ec 67 0c 0d 00 5d [ ]*risbhg %r6,%r7,12,13
.*: ec 67 0c 0d 0e 51 [ ]*risblg %r6,%r7,12,13,14
+.*: ec 67 0c 0d 00 51 [ ]*risblg %r6,%r7,12,13
.*: e3 67 8a 4d fe c3 [ ]*stch %r6,-5555\(%r7,%r8\)
.*: e3 67 8a 4d fe c7 [ ]*sthh %r6,-5555\(%r7,%r8\)
.*: e3 67 8a 4d fe cb [ ]*stfh %r6,-5555\(%r7,%r8\)
diff --git a/gas/testsuite/gas/s390/zarch-z196.s b/gas/testsuite/gas/s390/zarch-z196.s
index 31be5a62dba..213c2a1e676 100644
--- a/gas/testsuite/gas/s390/zarch-z196.s
+++ b/gas/testsuite/gas/s390/zarch-z196.s
@@ -23,7 +23,9 @@ foo:
llch %r6,-5555(%r7,%r8)
llhh %r6,-5555(%r7,%r8)
risbhg %r6,%r7,12,13,14
+ risbhg %r6,%r7,12,13
risblg %r6,%r7,12,13,14
+ risblg %r6,%r7,12,13
stch %r6,-5555(%r7,%r8)
sthh %r6,-5555(%r7,%r8)
stfh %r6,-5555(%r7,%r8)
diff --git a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d
index 96bf59b9fb0..57d7becdcdf 100644
--- a/gas/testsuite/gas/s390/zarch-zEC12.d
+++ b/gas/testsuite/gas/s390/zarch-zEC12.d
@@ -47,8 +47,11 @@ Disassembly of section .text:
.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
.*: ec 67 0c 0d 0e 59 [ ]*risbgn %r6,%r7,12,13,14
+.*: ec 67 0c 0d 00 59 [ ]*risbgn %r6,%r7,12,13
.*: ec 67 0c bc 0e 59 [ ]*risbgnz %r6,%r7,12,60,14
+.*: ec 67 0c bc 00 59 [ ]*risbgnz %r6,%r7,12,60
.*: ec 67 0c 94 0e 59 [ ]*risbgnz %r6,%r7,12,20,14
+.*: ec 67 0c 94 00 59 [ ]*risbgnz %r6,%r7,12,20
.*: ed 0f 8f a0 6d aa [ ]*cdzt %f6,4000\(16,%r8\),13
.*: ed 21 8f a0 4d ab [ ]*cxzt %f4,4000\(34,%r8\),13
.*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13
@@ -56,16 +59,11 @@ Disassembly of section .text:
.*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12
.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9
.*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1
-.*: c5 a0 0c 00 00 0c [ ]*bprp 10,136 <bar>,136 <bar>
+.*: c5 a0 0c 00 00 0c [ ]*bprp 10,148 <bar>,148 <bar>
*([\da-f]+): c5 a0 00 00 00 00 [ ]*bprp 10,\1 <foo\+0x\1>,\1 <foo\+0x\1>
-[ ]*125: R_390_PLT12DBL bar\+0x1
-[ ]*127: R_390_PLT24DBL bar\+0x3
+[ ]*137: R_390_PLT12DBL bar\+0x1
+[ ]*139: R_390_PLT24DBL bar\+0x3
*([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 <foo\+0x\1>,0
-[ ]*12e: R_390_PLT16DBL bar\+0x4
+[ ]*140: R_390_PLT16DBL bar\+0x4
*([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 <foo\+0x\1>,0
-[ ]*134: R_390_PC16DBL baz\+0x4
-
-
-0000000000000136 <bar>:
-
-.*: 07 07 [ ]*nopr %r7
+[ ]*146: R_390_PC16DBL baz\+0x4
diff --git a/gas/testsuite/gas/s390/zarch-zEC12.s b/gas/testsuite/gas/s390/zarch-zEC12.s
index 03b577e4830..3a30e8d72bf 100644
--- a/gas/testsuite/gas/s390/zarch-zEC12.s
+++ b/gas/testsuite/gas/s390/zarch-zEC12.s
@@ -44,8 +44,11 @@ foo:
clgtnh %r6,-5555(%r7)
risbgn %r6,%r7,12,13,14
+ risbgn %r6,%r7,12,13
risbgn %r6,%r7,12,188,14
+ risbgn %r6,%r7,12,188
risbgnz %r6,%r7,12,20,14
+ risbgnz %r6,%r7,12,20
cdzt %f6,4000(16,%r8),13
cxzt %f4,4000(34,%r8),13
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index b7efa813e47..9aeb2cc7ad1 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -305,6 +305,7 @@ b30d debr RRE_FF "divide short bfp" g5 esa,zarch
ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch
b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch
b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch
+# efpc and sfpc have only one operand; retain RR register format for compatibility
b38c efpc RRE_RR "extract fpc" g5 esa,zarch optparm
b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch
b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch
@@ -348,6 +349,7 @@ b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch
ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch
b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch
ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch
+# efpc and sfpc have only one operand; retain RR register format for compatibility
b384 sfpc RRE_RR "set fpc" g5 esa,zarch optparm
b299 srnm S_RD "set rounding mode" g5 esa,zarch
b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch
@@ -966,11 +968,11 @@ c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch
c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch
e30000000036 pfd RXY_URRD "prefetch data" z10 zarch
c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch
-ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch
-ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
-ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
-ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
-ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
+ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm
+ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm
+ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm
+ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm
+ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm
c40f strl RIL_RP "store relative long (32)" z10 zarch
c40b stgrl RIL_RP "store relative long (64)" z10 zarch
c407 sthrl RIL_RP "store halfword relative long" z10 zarch
@@ -1014,8 +1016,8 @@ e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch
e300000000ca lfh RXY_RRRD "load high" z196 zarch
e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch
e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch
-ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch
-ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch
+ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm
+ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm
e300000000c3 stch RXY_RRRD "store character high" z196 zarch
e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch
e300000000cb stfh RXY_RRRD "store high" z196 zarch
@@ -1153,8 +1155,8 @@ eb0000000023 clt RSY_RURD "compare logical and trap 32 bit reg-mem" zEC12 zarch
eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zarch
eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
-ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
-ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
+ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch optparm
+ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch optparm
ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
--
2.47.0

532
SOURCES/binutils-s390-arch15-part-05.patch
Unescape View File

@ -0,0 +1,532 @@
From 2bf1f788bd7941375af27741715af645faa1cee6 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 23 Nov 2023 15:48:15 +0100
Subject: [PATCH] s390: Add missing extended mnemonics
Commit: aab23df73e55
Add extended mnemonics specified in the z/Architecture Principles of
Operation [1] and z/Architecture Reference Summary [2], that were
previously missing from the opcode table.
The following added extended mnemonics are synonyms to a base mnemonic
and therefore disassemble into their base mnemonic:
jc, jcth, lfi, llgfi, llghi
The following added extended mnemonics are more specific than their base
mnemonic and therefore disassemble into the added extended mnemonic:
risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
The following added extended mnemonics are more specific than their base
mnemonic, but disassemble into their base mnemonic due to design
constraints:
notr, notgr
The missing extended mnemonic jl* conditional jump long flavors cannot
be added, as they would clash with the existing non-standard extended
mnemonic j* conditional jump flavors jle and jlh. The missing extended
mnemonic jlc jump long conditional is not added, as the related jl*
flavors cannot be added.
Note that these missing jl* conditional jump long flavors are already
defined as non-standard jg* flavors instead. While the related missing
extended mnemonic jlc could be added as non-standard jgc instead it is
forgone in favor of not adding further non-standard mnemonics.
The missing extended mnemonics sllhh, sllhl, slllh, srlhh, srlhl, and
srllh cannot be implemented using the current design, as they require
computed operands. For that reason the following missing extended
mnemonics are not added as well, as they fall into the same category of
instructions that operate on high and low words of registers. They
should better be added together, not to confuse the user, which of those
instructions are currently implemented or not.
lhhr, lhlr, llhfr, llchhr, llchlr, llclhr, llhhhr, llhhlr, llhlhr,
nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr
[1] IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
[2] IBM z/Architecture Reference Summary, SA22-7871-11,
https://www.ibm.com/support/pages/sites/default/files/2022-09/SA22-7871-11.pdf
opcodes/
* s390-opc.c: Define operand formats R_CP16_28, U6_18, and
U5_27. Define instruction formats RIE_RRUUU3, RIE_RRUUU4,
and RRF_R0RR4.
* s390-opc.txt: Add extended mnemonics jc, jcth, lfi, llgfi,
llghi, notgr, notr, risbhgz, risblgz, rnsbgt, rosbgt, and
rxsbgt.
gas/
* config/tc-s390.c: Add support to insert operand for format
R_CP16_28, reusing existing logic for format V_CP16_12.
* testsuite/gas/s390/esa-g5.s: Add test for extended mnemonic
jc.
* testsuite/gas/s390/esa-g5.d: Likewise.
* testsuite/gas/s390/zarch-z900.s: Add test for extended
mnemonic llghi.
* testsuite/gas/s390/zarch-z900.d: Likewise.
* testsuite/gas/s390/zarch-z9-109.s: Add tests for extended
mnemonics lfi and llgfi.
* testsuite/gas/s390/zarch-z9-109.d: Likewise.
* testsuite/gas/s390/zarch-z10.s: Add tests for extended
mnemonics rnsbgt, rosbgt, and rxsbgt.
* testsuite/gas/s390/zarch-z10.d: Likewise.
* testsuite/gas/s390/zarch-z196.s: Add tests for extended
mnemonics jcth, risbhgz, and risblgz.
* testsuite/gas/s390/zarch-z196.d: Likewise.
* testsuite/gas/s390/zarch-arch13.s: Add tests for extended
mnemonics notr and notgr.
* testsuite/gas/s390/zarch-arch13.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
gas/config/tc-s390.c | 12 ++++++++----
gas/testsuite/gas/s390/esa-g5.d | 1 +
gas/testsuite/gas/s390/esa-g5.s | 1 +
gas/testsuite/gas/s390/zarch-arch13.d | 4 ++++
gas/testsuite/gas/s390/zarch-arch13.s | 4 ++++
gas/testsuite/gas/s390/zarch-z10.d | 12 ++++++++++++
gas/testsuite/gas/s390/zarch-z10.s | 12 ++++++++++++
gas/testsuite/gas/s390/zarch-z196.d | 10 +++++++++-
gas/testsuite/gas/s390/zarch-z196.s | 9 +++++++++
gas/testsuite/gas/s390/zarch-z9-109.d | 2 ++
gas/testsuite/gas/s390/zarch-z9-109.s | 2 ++
gas/testsuite/gas/s390/zarch-z900.d | 5 +++--
gas/testsuite/gas/s390/zarch-z900.s | 1 +
opcodes/s390-opc.c | 22 +++++++++++++++++-----
opcodes/s390-opc.txt | 14 ++++++++++++++
15 files changed, 99 insertions(+), 12 deletions(-)
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 765a9a2e6bd..d601618d9dc 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -699,13 +699,17 @@ s390_insert_operand (unsigned char *insn,
if (operand->flags & S390_OPERAND_OR8)
uval |= 8;
- /* Duplicate the operand at bit pos 12 to 16. */
+ /* Duplicate the GPR/VR operand at bit pos 12 to 16. */
if (operand->flags & S390_OPERAND_CP16)
{
- /* Copy VR operand at bit pos 12 to bit pos 16. */
+ /* Copy GPR/VR operand at bit pos 12 to bit pos 16. */
insn[2] |= uval << 4;
- /* Copy the flag in the RXB field. */
- insn[4] |= (insn[4] & 4) >> 1;
+
+ if (operand->flags & S390_OPERAND_VR)
+ {
+ /* Copy the VR flag in the RXB field. */
+ insn[4] |= (insn[4] & 4) >> 1;
+ }
}
/* Insert fragments of the operand byte for byte. */
diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 7422e88b127..d276af1a70d 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -80,6 +80,7 @@ Disassembly of section .text:
*([\da-f]+): a7 95 00 00 [ ]*bras %r9,\1 <foo\+0x\1>
*([\da-f]+): a7 65 00 00 [ ]*bras %r6,\1 <foo\+0x\1>
*([\da-f]+): a7 64 00 00 [ ]*jlh \1 <foo\+0x\1>
+ *([\da-f]+): a7 64 00 00 [ ]*jlh \1 <foo\+0x\1>
*([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 <foo\+0x\1>
*([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 <foo\+0x\1>
*([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 <foo\+0x\1>
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index ee3d6319b19..2901a866ec9 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -74,6 +74,7 @@ foo:
bras %r9,.
jas %r6,.
brc 6,.
+ jc 6,.
brct 6,.
jct %r6,.
brxh %r6,%r9,.
diff --git a/gas/testsuite/gas/s390/zarch-arch13.d b/gas/testsuite/gas/s390/zarch-arch13.d
index fecbeb548c0..3ebdd9c17f3 100644
--- a/gas/testsuite/gas/s390/zarch-arch13.d
+++ b/gas/testsuite/gas/s390/zarch-arch13.d
@@ -12,7 +12,11 @@ Disassembly of section .text:
.*: b9 74 b0 69 [ ]*nnrk %r6,%r9,%r11
.*: b9 64 b0 69 [ ]*nngrk %r6,%r9,%r11
.*: b9 76 b0 69 [ ]*nork %r6,%r9,%r11
+.*: b9 76 70 67 [ ]*nork %r6,%r7,%r7
+.*: b9 76 70 67 [ ]*nork %r6,%r7,%r7
.*: b9 66 b0 69 [ ]*nogrk %r6,%r9,%r11
+.*: b9 66 70 67 [ ]*nogrk %r6,%r7,%r7
+.*: b9 66 70 67 [ ]*nogrk %r6,%r7,%r7
.*: b9 77 b0 69 [ ]*nxrk %r6,%r9,%r11
.*: b9 67 b0 69 [ ]*nxgrk %r6,%r9,%r11
.*: b9 75 b0 69 [ ]*ocrk %r6,%r9,%r11
diff --git a/gas/testsuite/gas/s390/zarch-arch13.s b/gas/testsuite/gas/s390/zarch-arch13.s
index 9563a1b4698..a830b20b3a5 100644
--- a/gas/testsuite/gas/s390/zarch-arch13.s
+++ b/gas/testsuite/gas/s390/zarch-arch13.s
@@ -6,7 +6,11 @@ foo:
nnrk %r6,%r9,%r11
nngrk %r6,%r9,%r11
nork %r6,%r9,%r11
+ nork %r6,%r7,%r7
+ notr %r6,%r7
nogrk %r6,%r9,%r11
+ nogrk %r6,%r7,%r7
+ notgr %r6,%r7
nxrk %r6,%r9,%r11
nxgrk %r6,%r9,%r11
ocrk %r6,%r9,%r11
diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
index 4aca8372363..4a051533f93 100644
--- a/gas/testsuite/gas/s390/zarch-z10.d
+++ b/gas/testsuite/gas/s390/zarch-z10.d
@@ -361,10 +361,22 @@ Disassembly of section .text:
*([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220
+.*: ec 67 92 dc e6 54 [ ]*rnsbgt %r6,%r7,18,220,230
+.*: ec 67 92 dc 00 54 [ ]*rnsbgt %r6,%r7,18,220
+.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38
+.*: ec 67 92 1c 00 54 [ ]*rnsbgt %r6,%r7,18,28
.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220
+.*: ec 67 92 dc e6 57 [ ]*rxsbgt %r6,%r7,18,220,230
+.*: ec 67 92 dc 00 57 [ ]*rxsbgt %r6,%r7,18,220
+.*: ec 67 92 1c 26 57 [ ]*rxsbgt %r6,%r7,18,28,38
+.*: ec 67 92 1c 00 57 [ ]*rxsbgt %r6,%r7,18,28
.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220
+.*: ec 67 92 dc e6 56 [ ]*rosbgt %r6,%r7,18,220,230
+.*: ec 67 92 dc 00 56 [ ]*rosbgt %r6,%r7,18,220
+.*: ec 67 92 1c 26 56 [ ]*rosbgt %r6,%r7,18,28,38
+.*: ec 67 92 1c 00 56 [ ]*rosbgt %r6,%r7,18,28
.*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230
.*: ec 67 d2 14 00 55 [ ]*risbg %r6,%r7,210,20
.*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230
diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s
index 3ed61a4f0fd..45bb8944793 100644
--- a/gas/testsuite/gas/s390/zarch-z10.s
+++ b/gas/testsuite/gas/s390/zarch-z10.s
@@ -355,10 +355,22 @@ foo:
pfdrl 10,.
rnsbg %r6,%r7,210,220,230
rnsbg %r6,%r7,210,220
+ rnsbg %r6,%r7,146,220,230
+ rnsbg %r6,%r7,146,220
+ rnsbgt %r6,%r7,18,28,38
+ rnsbgt %r6,%r7,18,28
rxsbg %r6,%r7,210,220,230
rxsbg %r6,%r7,210,220
+ rxsbg %r6,%r7,146,220,230
+ rxsbg %r6,%r7,146,220
+ rxsbgt %r6,%r7,18,28,38
+ rxsbgt %r6,%r7,18,28
rosbg %r6,%r7,210,220,230
rosbg %r6,%r7,210,220
+ rosbg %r6,%r7,146,220,230
+ rosbg %r6,%r7,146,220
+ rosbgt %r6,%r7,18,28,38
+ rosbgt %r6,%r7,18,28
risbg %r6,%r7,210,20,230
risbg %r6,%r7,210,20
risbg %r6,%r7,210,188,230
diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d
index b9db65f43ee..ac2478d6219 100644
--- a/gas/testsuite/gas/s390/zarch-z196.d
+++ b/gas/testsuite/gas/s390/zarch-z196.d
@@ -14,6 +14,7 @@ Disassembly of section .text:
.*: cc 6a 00 00 fd e8 [ ]*alsih %r6,65000
.*: cc 6b 00 00 fd e8 [ ]*alsihn %r6,65000
*([\da-f]+): cc 66 00 00 00 00 [ ]*brcth %r6,\1 <foo\+0x\1>
+ *([\da-f]+): cc 66 00 00 00 00 [ ]*brcth %r6,\1 <foo\+0x\1>
.*: b9 cd 00 67 [ ]*chhr %r6,%r7
.*: b9 dd 00 67 [ ]*chlr %r6,%r7
.*: e3 67 85 b3 01 cd [ ]*chf %r6,5555\(%r7,%r8\)
@@ -30,8 +31,16 @@ Disassembly of section .text:
.*: e3 67 8a 4d fe c6 [ ]*llhh %r6,-5555\(%r7,%r8\)
.*: ec 67 0c 0d 0e 5d [ ]*risbhg %r6,%r7,12,13,14
.*: ec 67 0c 0d 00 5d [ ]*risbhg %r6,%r7,12,13
+.*: ec 67 0c 8d 0e 5d [ ]*risbhgz %r6,%r7,12,13,14
+.*: ec 67 0c 8d 00 5d [ ]*risbhgz %r6,%r7,12,13
+.*: ec 67 0c 8d 0e 5d [ ]*risbhgz %r6,%r7,12,13,14
+.*: ec 67 0c 8d 00 5d [ ]*risbhgz %r6,%r7,12,13
.*: ec 67 0c 0d 0e 51 [ ]*risblg %r6,%r7,12,13,14
.*: ec 67 0c 0d 00 51 [ ]*risblg %r6,%r7,12,13
+.*: ec 67 0c 8d 0e 51 [ ]*risblgz %r6,%r7,12,13,14
+.*: ec 67 0c 8d 00 51 [ ]*risblgz %r6,%r7,12,13
+.*: ec 67 0c 8d 0e 51 [ ]*risblgz %r6,%r7,12,13,14
+.*: ec 67 0c 8d 00 51 [ ]*risblgz %r6,%r7,12,13
.*: e3 67 8a 4d fe c3 [ ]*stch %r6,-5555\(%r7,%r8\)
.*: e3 67 8a 4d fe c7 [ ]*sthh %r6,-5555\(%r7,%r8\)
.*: e3 67 8a 4d fe cb [ ]*stfh %r6,-5555\(%r7,%r8\)
@@ -261,4 +270,3 @@ Disassembly of section .text:
.*: b9 2c 00 00 [ ]*pcc
.*: b9 2d 60 59 [ ]*kmctr %r5,%r6,%r9
.*: b9 28 00 00 [ ]*pckmo
-.*: 07 07 [ ]*nopr %r7
diff --git a/gas/testsuite/gas/s390/zarch-z196.s b/gas/testsuite/gas/s390/zarch-z196.s
index 213c2a1e676..bd594259532 100644
--- a/gas/testsuite/gas/s390/zarch-z196.s
+++ b/gas/testsuite/gas/s390/zarch-z196.s
@@ -8,6 +8,7 @@ foo:
alsih %r6,65000
alsihn %r6,65000
brcth %r6,.
+ jcth %r6,.
chhr %r6,%r7
chlr %r6,%r7
chf %r6,5555(%r7,%r8)
@@ -24,8 +25,16 @@ foo:
llhh %r6,-5555(%r7,%r8)
risbhg %r6,%r7,12,13,14
risbhg %r6,%r7,12,13
+ risbhg %r6,%r7,12,141,14
+ risbhg %r6,%r7,12,141
+ risbhgz %r6,%r7,12,13,14
+ risbhgz %r6,%r7,12,13
risblg %r6,%r7,12,13,14
risblg %r6,%r7,12,13
+ risblg %r6,%r7,12,141,14
+ risblg %r6,%r7,12,141
+ risblgz %r6,%r7,12,13,14
+ risblgz %r6,%r7,12,13
stch %r6,-5555(%r7,%r8)
sthh %r6,-5555(%r7,%r8)
stfh %r6,-5555(%r7,%r8)
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d
index 5a9717c24ac..012270e733f 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109.d
+++ b/gas/testsuite/gas/s390/zarch-z9-109.d
@@ -36,6 +36,7 @@ Disassembly of section .text:
.*: b9 85 00 69 [ ]*llghr %r6,%r9
.*: c0 6e ff ff ff ff [ ]*llihf %r6,4294967295
.*: c0 6f ff ff ff ff [ ]*llilf %r6,4294967295
+.*: c0 6f ff ff ff ff [ ]*llilf %r6,4294967295
.*: c0 6c ff ff ff ff [ ]*oihf %r6,4294967295
.*: c0 6d ff ff ff ff [ ]*oilf %r6,4294967295
.*: c2 65 ff ff ff ff [ ]*slfi %r6,4294967295
@@ -70,4 +71,5 @@ Disassembly of section .text:
.*: ed 95 af ff 60 38 [ ]*mayl %f6,%f9,4095\(%r5,%r10\)
.*: b9 be 00 67 [ ]*srstu %r6,%r7
.*: d0 16 5f ff ad 05 [ ]*trtr 4095\(23,%r5\),3333\(%r10\)
+.*: c0 69 ff ff ff ff [ ]*iilf %r6,4294967295
.*: 07 07 [ ]*nopr %r7
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s
index 10d77ac673e..22dca84fd32 100644
--- a/gas/testsuite/gas/s390/zarch-z9-109.s
+++ b/gas/testsuite/gas/s390/zarch-z9-109.s
@@ -30,6 +30,7 @@ foo:
llghr %r6,%r9
llihf %r6,4294967295
llilf %r6,4294967295
+ llgfi %r6,4294967295
oihf %r6,4294967295
oilf %r6,4294967295
slfi %r6,4294967295
@@ -64,3 +65,4 @@ foo:
mayl %f6,%f9,4095(%r5,%r10)
srstu %r6,%r7
trtr 4095(23,%r5),3333(%r10)
+ lfi %r6,4294967295
diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d
index 93aee212785..88751711c1b 100644
--- a/gas/testsuite/gas/s390/zarch-z900.d
+++ b/gas/testsuite/gas/s390/zarch-z900.d
@@ -85,6 +85,7 @@ Disassembly of section .text:
.*: a5 9d ff ff [ ]*llihl %r9,65535
.*: a5 9e ff ff [ ]*llilh %r9,65535
.*: a5 9f ff ff [ ]*llill %r9,65535
+.*: a5 9f ff ff [ ]*llill %r9,65535
.*: ef 96 5f ff af ff [ ]*lmd %r9,%r6,4095\(%r5\),4095\(%r10\)
.*: eb 96 5f ff 00 04 [ ]*lmg %r9,%r6,4095\(%r5\)
.*: eb 96 5f ff 00 96 [ ]*lmh %r9,%r6,4095\(%r5\)
@@ -153,6 +154,6 @@ Disassembly of section .text:
*([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 <foo\+0x\1>
*([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 <foo\+0xffffffff0+\1>
*([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 <foo\+0xffffffff0+\1>
-.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d0 <foo\+0x1000002d0>
-.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d6 <foo\+0x1000002d6>
+.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d4 <foo\+0x1000002d4>
+.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002da <foo\+0x1000002da>
.*: 07 07 [ ]*nopr %r7
diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s
index 22fa1da5a30..8890fbb78a0 100644
--- a/gas/testsuite/gas/s390/zarch-z900.s
+++ b/gas/testsuite/gas/s390/zarch-z900.s
@@ -79,6 +79,7 @@ foo:
llihl %r9,65535
llilh %r9,65535
llill %r9,65535
+ llghi %r9,65535
lmd %r9,%r6,4095(%r5),4095(%r10)
lmg %r9,%r6,4095(%r5)
lmh %r9,%r6,4095(%r5)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index b52fc8c3b62..0427bd8b2e0 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -62,7 +62,9 @@ const struct s390_operand s390_operands[] =
{ 4, 24, S390_OPERAND_GPR },
#define R_28 (R_24 + 1) /* GPR starting at position 28 */
{ 4, 28, S390_OPERAND_GPR },
-#define R_32 (R_28 + 1) /* GPR starting at position 32 */
+#define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */
+ { 4, 28, S390_OPERAND_GPR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */
+#define R_32 (R_CP16_28+1) /* GPR starting at position 32 */
{ 4, 32, S390_OPERAND_GPR },
/* General purpose register pair operands. */
@@ -222,9 +224,13 @@ const struct s390_operand s390_operands[] =
{ 4, 36, 0 },
#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
-#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
+#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */
+ { 6, 18, 0 },
+#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
-#define U6_26 (U8_16 + 1) /* 6 bit unsigned value starting at 26 */
+#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */
+ { 5, 27, 0 },
+#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */
{ 6, 26, 0 },
#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
@@ -289,7 +295,7 @@ static inline void unused_s390_operands_static_asserts(void)
p - pc relative
r - general purpose register
re - gpr extended operand, a valid general purpose register pair
- u - unsigned integer, 4, 8, 16 or 32 bit
+ u - unsigned integer, 4, 6, 8, 16 or 32 bit
m - mode field, 4 bit
0 - operand skipped.
The order of the letters reflects the layout of the format in
@@ -325,7 +331,9 @@ static inline void unused_s390_operands_static_asserts(void)
#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
+#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */
+#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */
+#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
@@ -374,6 +382,7 @@ static inline void unused_s390_operands_static_asserts(void)
#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */
#define INSTR_RRF_R0RER 4, { RE_24,R_28,R_16,0,0,0 } /* e.g. mgrk */
#define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */
+#define INSTR_RRF_R0RR4 4, { R_24,R_CP16_28,0,0,0,0 } /* e.g. notr */
#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
@@ -550,6 +559,8 @@ static inline void unused_s390_operands_static_asserts(void)
#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
+#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff }
+#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -598,6 +609,7 @@ static inline void unused_s390_operands_static_asserts(void)
#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_R0RER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_R0RR4 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 9aeb2cc7ad1..674c0cf1987 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -272,6 +272,7 @@ a701 tml RI_RU "test under mask low" g5 esa,zarch
4700 nop RX_0RRD "no operation" g5 esa,zarch optparm
4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch
47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
+a704 jc RI_UP "conditional jump" g5 esa,zarch
a704 jnop RI_0P "nop jump" g5 esa,zarch
a704 j*8 RI_0P "conditional jump" g5 esa,zarch
a704 br*8 RI_0P "conditional jump" g5 esa,zarch
@@ -473,8 +474,10 @@ eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch
a702 tmhh RI_RU "test under mask high high" z900 zarch
a703 tmhl RI_RU "test under mask high low" z900 zarch
c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
+# jlc omitted due to missing jl* (see jl*8) and not added as non-standard jgc
c004 jgnop RIL_0P "nop jump long" z900 esa,zarch
c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch
+# jl*8 omitted due to clash with non-standard j*8 flavors jle and jlh; exists as non-standard jg*8 instead
c004 br*8l RIL_0P "conditional jump long" z900 esa,zarch
c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch
c0f4 brul RIL_0P "unconditional jump long" z900 esa,zarch
@@ -523,6 +526,7 @@ a50c llihh RI_RU "load logical immediate high high" z900 zarch
a50d llihl RI_RU "load logical immediate high low" z900 zarch
a50e llilh RI_RU "load logical immediate low high" z900 zarch
a50f llill RI_RU "load logical immediate low low" z900 zarch
+a50f llghi RI_RU "load logical immediate" z900 zarch
b2b1 stfl S_RD "store facility list" z900 esa,zarch
b2b2 lpswe S_RD "load psw extended" z900 zarch
b90d dsgr RRE_RER "divide single 64" z900 zarch
@@ -750,6 +754,7 @@ c006 xihf RIL_RU "exclusive or immediate high" z9-109 zarch
c007 xilf RIL_RU "exclusive or immediate low" z9-109 zarch
c008 iihf RIL_RU "insert immediate high" z9-109 zarch
c009 iilf RIL_RU "insert immediate low" z9-109 zarch
+c009 lfi RIL_RU "insert immediate 32" z9-109 zarch
# z9-109 misc instruction
b983 flogr RRE_RER "find leftmost one" z9-109 zarch
e30000000012 lt RXY_RRRD "load and test 32" z9-109 zarch
@@ -767,6 +772,7 @@ b995 llhr RRE_RR "load logical halfword 32" z9-109 zarch
b985 llghr RRE_RR "load logical halfword 64" z9-109 zarch
c00e llihf RIL_RU "load logical immediate high" z9-109 zarch
c00f llilf RIL_RU "load logical immediate low" z9-109 zarch
+c00f llgfi RIL_RU "load logical immediate" z9-109 zarch
c00c oihf RIL_RU "or immediate high" z9-109 zarch
c00d oilf RIL_RU "or immediate low" z9-109 zarch
c205 slfi RIL_RU "subtract logical immediate 32" z9-109 zarch
@@ -969,8 +975,11 @@ c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch
e30000000036 pfd RXY_URRD "prefetch data" z10 zarch
c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch
ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm
+ec0080000054 rnsbgt RIE_RRUUU4 "rotate then and selected bits and test results" z10 zarch optparm
ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm
+ec0080000057 rxsbgt RIE_RRUUU4 "rotate then exclusive or selected bits and test results" z10 zarch optparm
ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm
+ec0080000056 rosbgt RIE_RRUUU4 "rotate then or selected bits and test results" z10 zarch optparm
ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm
ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm
c40f strl RIL_RP "store relative long (32)" z10 zarch
@@ -1003,6 +1012,7 @@ b9da alhhlr RRF_R0RR2 "add logical high low" z196 zarch
cc0a alsih RIL_RI "add logical with signed immediate high with cc" z196 zarch
cc0b alsihn RIL_RI "add logical with signed immediate high no cc" z196 zarch
cc06 brcth RIL_RP "branch relative on count high" z196 zarch
+cc06 jcth RIL_RP "jump on count high" z196 zarch
b9cd chhr RRE_RR "compare high high" z196 zarch
b9dd chlr RRE_RR "compare high low" z196 zarch
e300000000cd chf RXY_RRRD "compare high" z196 zarch
@@ -1017,7 +1027,9 @@ e300000000ca lfh RXY_RRRD "load high" z196 zarch
e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch
e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch
ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm
+ec000080005d risbhgz RIE_RRUUU3 "rotate then insert selected bits high and zero remaining bits" z196 zarch optparm
ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm
+ec0000800051 risblgz RIE_RRUUU3 "rotate then insert selected bits low and zero remaining bits" z196 zarch optparm
e300000000c3 stch RXY_RRRD "store character high" z196 zarch
e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch
e300000000cb stfh RXY_RRRD "store high" z196 zarch
@@ -1913,7 +1925,9 @@ e50a mvcrl SSE_RDRD "move right to left" arch13 zarch
b974 nnrk RRF_R0RR2 "nand 32 bit" arch13 zarch
b964 nngrk RRF_R0RR2 "nand 64 bit" arch13 zarch
b976 nork RRF_R0RR2 "nor 32 bit" arch13 zarch
+b976 notr RRF_R0RR4 "not 32 bit" arch13 zarch
b966 nogrk RRF_R0RR2 "nor 64 bit" arch13 zarch
+b966 notgr RRF_R0RR4 "not 64 bit" arch13 zarch
b977 nxrk RRF_R0RR2 "not exclusive or 32 bit" arch13 zarch
b967 nxgrk RRF_R0RR2 "not exclusive or 64 bit" arch13 zarch
b975 ocrk RRF_R0RR2 "or with complement 32 bit" arch13 zarch
--
2.47.0

36
SOURCES/binutils-s390-arch15-part-06.patch
Unescape View File

@ -0,0 +1,36 @@
From 6e1d1b2e7b2e12e53fa287387fbbca9c56dc29d0 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 23 Nov 2023 15:48:59 +0100
Subject: [PATCH] s390: Correct prno instruction name
Commit: 31238493cc81
IBM z13 (arch11) introduced ppno (Perform Pseudorandom Number Operation).
IBM z14 (arch12) introduced prno (Perform Random Number Operation) and
deprecated ppno.
opcodes/
* s390-opc.txt: Correct prno instruction name.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
opcodes/s390-opc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 674c0cf1987..853758b96aa 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -1910,7 +1910,7 @@ e30000000049 stgsc RXY_RRRD "store guarded storage controls" arch12 zarch
b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch
-b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch
+b93c prno RRE_RR "perform random number operation" arch12 zarch
b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch
b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch
--
2.47.0

31
SOURCES/binutils-s390-arch15-part-07.patch
Unescape View File

@ -0,0 +1,31 @@
From 6c0c7d489bdf106d90b300aeb8d042c7b1ad3d2b Mon Sep 17 00:00:00 2001
From: Nick Clifton <nickc@redhat.com>
Date: Fri, 24 Nov 2023 08:10:12 +0000
Subject: [PATCH] Fix building for the s390 target with clang
Commit: adc54be82956
---
opcodes/s390-opc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 0427bd8b2e0..cbfdb3df0b7 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -262,9 +262,10 @@ const struct s390_operand s390_operands[] =
};
-static inline void unused_s390_operands_static_asserts(void)
+static inline void ATTRIBUTE_UNUSED
+unused_s390_operands_static_asserts (void)
{
- static_assert(ARRAY_SIZE(s390_operands) - 1 == J32_16);
+ static_assert (ARRAY_SIZE (s390_operands) - 1 == J32_16);
}
/* Macros used to form opcodes. */
--
2.47.0

100
SOURCES/binutils-s390-arch15-part-08.patch
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@ -0,0 +1,100 @@
From 8e194ff8cced7cd3924353d39706bd6656d654e2 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Wed, 20 Dec 2023 11:16:08 +0100
Subject: [PATCH] s390: Align letter case of instruction descriptions
Commit: 47ee40afbf8d
Change the bitwise operations names "and" and "or" to lower case. Change
the register name abbreviations "FPR", "GR", and "VR" to upper case.
opcodes/
* s390-opc.txt: Align letter case of instruction descriptions.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
opcodes/s390-opc.txt | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff -rup binutils.orig/opcodes/s390-opc.txt binutils-2.41/opcodes/s390-opc.txt
--- binutils.orig/opcodes/s390-opc.txt 2024-11-12 16:44:14.887824730 +0000
+++ binutils-2.41/opcodes/s390-opc.txt 2024-11-12 16:44:23.719849187 +0000
@@ -144,14 +144,14 @@ d3 mvz SS_L0RDRD "move zones" g5 esa,zar
67 mxd RX_FERRD "multiply (long to ext.)" g5 esa,zarch
27 mxdr RR_FEF "multiply (long to ext.)" g5 esa,zarch
26 mxr RR_FEFE "multiply (ext.)" g5 esa,zarch
-54 n RX_RRRD "AND" g5 esa,zarch
-d4 nc SS_L0RDRD "AND" g5 esa,zarch
-94 ni SI_URD "AND" g5 esa,zarch
-14 nr RR_RR "AND" g5 esa,zarch
-56 o RX_RRRD "OR" g5 esa,zarch
-d6 oc SS_L0RDRD "OR" g5 esa,zarch
-96 oi SI_URD "OR" g5 esa,zarch
-16 or RR_RR "OR" g5 esa,zarch
+54 n RX_RRRD "and" g5 esa,zarch
+d4 nc SS_L0RDRD "and" g5 esa,zarch
+94 ni SI_URD "and" g5 esa,zarch
+14 nr RR_RR "and" g5 esa,zarch
+56 o RX_RRRD "or" g5 esa,zarch
+d6 oc SS_L0RDRD "or" g5 esa,zarch
+96 oi SI_URD "or" g5 esa,zarch
+16 or RR_RR "or" g5 esa,zarch
f2 pack SS_LLRDRD "pack" g5 esa,zarch
b248 palb RRE_00 "purge ALB" g5 esa,zarch
b218 pc S_RD "program call" g5 esa,zarch
@@ -215,8 +215,8 @@ b6 stctl RS_CCRD "store control" g5 esa,
40 sth RX_RRRD "store halfword" g5 esa,zarch
b202 stidp S_RD "store CPU id" g5 esa,zarch
90 stm RS_RRRD "store multiple" g5 esa,zarch
-ac stnsm SI_URD "store then AND system mask" g5 esa,zarch
-ad stosm SI_URD "store then OR system mask" g5 esa,zarch
+ac stnsm SI_URD "store then and system mask" g5 esa,zarch
+ad stosm SI_URD "store then or system mask" g5 esa,zarch
b209 stpt S_RD "store CPU timer" g5 esa,zarch
b211 stpx S_RD "store prefix" g5 esa,zarch
b234 stsch S_RD "store subchannel" g5 esa,zarch
@@ -239,10 +239,10 @@ dd trt SS_L0RDRD "translate and test" g5
b235 tsch S_RD "test subchannel" g5 esa,zarch
f3 unpk SS_LLRDRD "unpack" g5 esa,zarch
0102 upt E "update tree" g5 esa,zarch
-57 x RX_RRRD "exclusive OR" g5 esa,zarch
-d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch
-97 xi SI_URD "exclusive OR" g5 esa,zarch
-17 xr RR_RR "exclusive OR" g5 esa,zarch
+57 x RX_RRRD "exclusive or" g5 esa,zarch
+d7 xc SS_L0RDRD "exclusive or" g5 esa,zarch
+97 xi SI_URD "exclusive or" g5 esa,zarch
+17 xr RR_RR "exclusive or" g5 esa,zarch
f8 zap SS_LLRDRD "zero and add" g5 esa,zarch
a70a ahi RI_RI "add halfword immediate" g5 esa,zarch
84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch
@@ -821,8 +821,8 @@ b370 lpdfr RRE_FF "load positive no cc"
b371 lndfr RRE_FF "load negative no cc" z9-ec zarch
b372 cpsdr RRF_F0FF2 "copy sign" z9-ec zarch
b373 lcdfr RRE_FF "load complement no cc" z9-ec zarch
-b3c1 ldgr RRE_FR "load fpr from gr" z9-ec zarch
-b3cd lgdr RRE_RF "load gr from fpr" z9-ec zarch
+b3c1 ldgr RRE_FR "load FPR from GR" z9-ec zarch
+b3cd lgdr RRE_RF "load GR from FPR" z9-ec zarch
b3d2 adtr RRR_F0FF "add long dfp" z9-ec zarch
b3da axtr RRR_FE0FEFE "add extended dfp" z9-ec zarch
b3e4 cdtr RRE_FF "compare long dfp" z9-ec zarch
@@ -1203,11 +1203,11 @@ e70000000040 vleib VRI_V0IU "vector load
e70000000041 vleih VRI_V0IU "vector load halfword element immediate" z13 zarch vx
e70000000043 vleif VRI_V0IU "vector load word element immediate" z13 zarch vx
e70000000042 vleig VRI_V0IU "vector load double word element immediate" z13 zarch vx
-e70000000021 vlgv VRS_RVRDU "vector load gr from vr element" z13 zarch vx
-e70000000021 vlgvb VRS_RVRD "vector load gr from vr byte element" z13 zarch vx
-e70000001021 vlgvh VRS_RVRD "vector load gr from vr halfword element" z13 zarch vx
-e70000002021 vlgvf VRS_RVRD "vector load gr from vr word element" z13 zarch vx
-e70000003021 vlgvg VRS_RVRD "vector load gr from vr double word element" z13 zarch vx
+e70000000021 vlgv VRS_RVRDU "vector load GR from VR element" z13 zarch vx
+e70000000021 vlgvb VRS_RVRD "vector load GR from VR byte element" z13 zarch vx
+e70000001021 vlgvh VRS_RVRD "vector load GR from VR halfword element" z13 zarch vx
+e70000002021 vlgvf VRS_RVRD "vector load GR from VR word element" z13 zarch vx
+e70000003021 vlgvg VRS_RVRD "vector load GR from VR double word element" z13 zarch vx
e70000000004 vllez VRX_VRRDU "vector load logical element and zero" z13 zarch vx
e70000000004 vllezb VRX_VRRD "vector load logical byte element and zero" z13 zarch vx
e70000001004 vllezh VRX_VRRD "vector load logical halfword element and zero" z13 zarch vx

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From 2ff609b4ce8f3142b4e5592116f28c83a07066c3 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Wed, 20 Dec 2023 11:16:38 +0100
Subject: [PATCH] s390: Provide IBM z16 (arch14) instruction descriptions
Commit: 72a045b9f300
Provide descriptions for instructions introduced with commit ba2b480f103
("IBM Z: Implement instruction set extensions"). This complements commit
69341966def ("IBM zSystems: Add support for z16 as CPU name."). Use
instruction names from IBM z/Architecture Principles of Operation [1] as
instruction description.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-opc.txt: Add descriptions for IBM z16 (arch14)
instructions.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
---
opcodes/s390-opc.txt | 66 +++++++++++++++++++++++++-------------------
1 file changed, 38 insertions(+), 28 deletions(-)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index ef4ef9dc517..a3117eeebc5 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2034,31 +2034,41 @@ e60000000052 vcvbg VRR_RV0UU "vector convert to binary 64 bit" arch13 zarch optp
b93a kdsa RRE_RR "compute digital signature authentication" arch13 zarch
-# arch14 instructions
-
-e60000000074 vschp VRR_VVV0U0U " " arch14 zarch
-e60000002074 vschsp VRR_VVV0U0 " " arch14 zarch
-e60000003074 vschdp VRR_VVV0U0 " " arch14 zarch
-e60000004074 vschxp VRR_VVV0U0 " " arch14 zarch
-e6000000007c vscshp VRR_VVV " " arch14 zarch
-e6000000007d vcsph VRR_VVV0U0 " " arch14 zarch
-e60000000051 vclzdp VRR_VV0U2 " " arch14 zarch
-e60000000070 vpkzr VRI_VVV0UU2 " " arch14 zarch
-e60000000072 vsrpr VRI_VVV0UU2 " " arch14 zarch
-e60000000054 vupkzh VRR_VV0U2 " " arch14 zarch
-e6000000005c vupkzl VRR_VV0U2 " " arch14 zarch
-
-b93b nnpa RRE_00 " " arch14 zarch
-e60000000056 vclfnh VRR_VV0UU2 " " arch14 zarch
-e6000000005e vclfnl VRR_VV0UU2 " " arch14 zarch
-e60000000075 vcrnf VRR_VVV0UU " " arch14 zarch
-e6000000005d vcfn VRR_VV0UU2 " " arch14 zarch
-e60000000055 vcnf VRR_VV0UU2 " " arch14 zarch
-
-b98B rdp RRF_RURR2 " " arch14 zarch optparm
-
-eb0000000071 lpswey SIY_RD " " arch14 zarch
-b200 lbear S_RD " " arch14 zarch
-b201 stbear S_RD " " arch14 zarch
-
-b28f qpaci S_RD " " arch14 zarch
+# arch14 (z16) instructions
+
+# Vector-Packed-Decimal-Enhancement Facility 2
+
+e60000000074 vschp VRR_VVV0U0U "decimal scale and convert to hfp" arch14 zarch
+e60000002074 vschsp VRR_VVV0U0 "decimal scale and convert to short hfp" arch14 zarch
+e60000003074 vschdp VRR_VVV0U0 "decimal scale and convert to long hfp" arch14 zarch
+e60000004074 vschxp VRR_VVV0U0 "decimal scale and convert to extended hfp" arch14 zarch
+e6000000007c vscshp VRR_VVV "decimal scale and convert and split to hfp" arch14 zarch
+e6000000007d vcsph VRR_VVV0U0 "vector convert hfp to scaled decimal" arch14 zarch
+e60000000051 vclzdp VRR_VV0U2 "vector count leading zero digits" arch14 zarch
+e60000000070 vpkzr VRI_VVV0UU2 "vector pack zoned register" arch14 zarch
+e60000000072 vsrpr VRI_VVV0UU2 "vector shift and round decimal register" arch14 zarch
+e60000000054 vupkzh VRR_VV0U2 "vector unpack zoned high" arch14 zarch
+e6000000005c vupkzl VRR_VV0U2 "vector unpack zoned low" arch14 zarch
+
+# Neural-Network-Processing-Assist Facility
+
+b93b nnpa RRE_00 "neural network processing assist" arch14 zarch
+e60000000056 vclfnh VRR_VV0UU2 "vector fp convert and lengthen from nnp high" arch14 zarch
+e6000000005e vclfnl VRR_VV0UU2 "vector fp convert and lengthen from nnp low" arch14 zarch
+e60000000075 vcrnf VRR_VVV0UU "vector fp convert and round to nnp" arch14 zarch
+e6000000005d vcfn VRR_VV0UU2 "vector fp convert from nnp" arch14 zarch
+e60000000055 vcnf VRR_VV0UU2 "vector fp convert to nnp" arch14 zarch
+
+# Reset-DAT-Protection Facility
+
+b98B rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm
+
+# BEAR-Enhancement Facility
+
+eb0000000071 lpswey SIY_RD "load PSW extended" arch14 zarch
+b200 lbear S_RD "load bear" arch14 zarch
+b201 stbear S_RD "store bear" arch14 zarch
+
+# Processor-Activity-Instrumentation Facility
+
+b28f qpaci S_RD "query processor activity counter information" arch14 zarch
--
2.47.0

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From 1afe02759f1569fb647b691d308c95efc2116b23 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Mon, 9 Sep 2024 17:05:28 +0200
Subject: [PATCH] s390: Align opcodes to lower-case
Commit: 307b615828bb
opcodes/
* s390-opc.txt (rdp): Change opcode to lower-case.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
opcodes/s390-opc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 1182e196059..4610a8fddd7 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2061,7 +2061,7 @@ e60000000055 vcnf VRR_VV0UU2 "vector fp convert to nnp" arch14 zarch
# Reset-DAT-Protection Facility
-b98B rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm
+b98b rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm
# BEAR-Enhancement Facility
--
2.47.0

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From a3f1e7c56a60573562e8578ae8b675ec1f4448e7 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 12 Sep 2024 15:06:06 +0200
Subject: [PATCH] s390: Simplify (dis)assembly of insn operands with const bits
Commit: a3a696bfd8b8
Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.
The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.
This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx
include/
* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
S390_OPERAND_OR8): Remove.
opcodes/
* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
respective insn fmt mask.
(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
mask.
* s390-dis.c (s390_print_insn_with_opcode): Mask constant
operand bits set in insn template of non-length unsigned
integer operands.
gas/
* config/tc-s390.c (s390_insert_operand): Do not OR constant
operand value bits.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
gas/config/tc-s390.c | 7 -------
include/opcode/s390.h | 4 ----
opcodes/s390-dis.c | 14 ++++++++------
opcodes/s390-opc.c | 26 +++++++++-----------------
4 files changed, 17 insertions(+), 34 deletions(-)
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 659c6af392b..75e1011f67b 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -795,13 +795,6 @@ s390_insert_operand (unsigned char *insn,
uval &= 0xf;
}
- if (operand->flags & S390_OPERAND_OR1)
- uval |= 1;
- if (operand->flags & S390_OPERAND_OR2)
- uval |= 2;
- if (operand->flags & S390_OPERAND_OR8)
- uval |= 8;
-
/* Duplicate the GPR/VR operand at bit pos 12 to 16. */
if (operand->flags & S390_OPERAND_CP16)
{
diff --git a/include/opcode/s390.h b/include/opcode/s390.h
index e5dfcb27570..8de03701172 100644
--- a/include/opcode/s390.h
+++ b/include/opcode/s390.h
@@ -193,8 +193,4 @@ extern const struct s390_operand s390_operands[];
#define S390_OPERAND_CP16 0x1000
-#define S390_OPERAND_OR1 0x2000
-#define S390_OPERAND_OR2 0x4000
-#define S390_OPERAND_OR8 0x8000
-
#endif /* S390_H */
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index ee2f2cb62ed..852d2f6ebb9 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -299,12 +299,14 @@ s390_print_insn_with_opcode (bfd_vma memaddr,
{
enum disassembler_style style;
- if (flags & S390_OPERAND_OR1)
- val.u &= ~1;
- if (flags & S390_OPERAND_OR2)
- val.u &= ~2;
- if (flags & S390_OPERAND_OR8)
- val.u &= ~8;
+ if (!(flags & S390_OPERAND_LENGTH))
+ {
+ union operand_value insn_opval;
+
+ /* Mask any constant operand bits set in insn template. */
+ insn_opval = s390_extract_operand (opcode->opcode, operand);
+ val.u &= ~insn_opval.u;
+ }
if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)
&& val.u == 0
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 10482fbc1e0..987004d7b07 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -208,17 +208,9 @@ const struct s390_operand s390_operands[] =
{ 4, 20, 0 },
#define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */
{ 4, 24, 0 },
-#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */
- { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */
-#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */
- { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */
- { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */
+#define U4_28 (U4_24+1) /* 4 bit unsigned value starting at 28 */
{ 4, 28, 0 },
-#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */
- { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */
-#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */
+#define U4_32 (U4_28+1) /* 4 bit unsigned value starting at 32 */
{ 4, 32, 0 },
#define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */
{ 4, 36, 0 },
@@ -512,23 +504,23 @@ unused_s390_operands_static_asserts (void)
#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */
#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */
#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */
-#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/
-#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/
-#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/
+#define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/
+#define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/
+#define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/
#define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */
#define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */
#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */
#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/
#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */
#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */
-#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */
+#define INSTR_VRR_VV0UU8 INSTR_VRR_VV0UU /* e.g. wcdgb */
#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */
#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */
#define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */
#define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/
-#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/
-#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/
-#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/
+#define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB /* e.g. vstrcbs*/
+#define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB /* e.g. vstrczb*/
+#define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB /* e.g. vstrczbs*/
#define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */
#define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */
#define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/
--
2.47.0

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From b8b60e2d0cb0ab1f235f082dbb8a4e8bc43aadf6 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Thu, 12 Sep 2024 15:06:06 +0200
Subject: [PATCH] s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints
Commit: 69371b2a1567
This leverages commit ("s390: Simplify (dis)assembly of insn operands
with const bits") to relax the operand constraints of the immediate
operand that contains the constant Z- or T-bit of the following extended
mnemonics:
risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
Previously those instructions were the only ones where the assembler
on s390 restricted the specification of the subject I3/I4 operand values
exactly according to their specification to an unsigned 6- or 5-bit
unsigned integer. For any other instructions the assembler allows to
specify any operand value allowed by the instruction format, regardless
of whether the instruction specification is more restrictive.
Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
with the constant operand bits being ORed during assembly.
Relax the instructions subject significant operand bit masks to only
consider the Z/T-bit as significant, so that the instructions get
disassembled as their *z or *t flavor regardless of whether any reserved
bits are set in addition to the Z/T-bit.
Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
the T-bit in operand I3, as they otherwise get disassembled as their
rnsbgt, rosbgt, and rxsbgt counterpart.
This aligns GNU Assembler to LLVM Assembler.
opcodes/
* s390-opc.c (U6_18, U5_27, U6_26): Remove.
(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
as INSTR_RIE_RRUUU while retaining insn fmt mask.
(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
Z/T-bit of I3/I4 operand as significant.
gas/testsuite/
* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.
Reported-by: Dominik Steenken <dost@de.ibm.com>
Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
gas/testsuite/gas/s390/zarch-z10.d | 12 ++++++------
gas/testsuite/gas/s390/zarch-z10.s | 12 ++++++------
opcodes/s390-opc.c | 24 +++++++++---------------
3 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
index 4a051533f93..beb057878d6 100644
--- a/gas/testsuite/gas/s390/zarch-z10.d
+++ b/gas/testsuite/gas/s390/zarch-z10.d
@@ -359,20 +359,20 @@ Disassembly of section .text:
.*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000
.*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
*([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
-.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220
+.*: ec 67 6e dc e6 54 [ ]*rnsbg %r6,%r7,110,220,230
+.*: ec 67 6e dc 00 54 [ ]*rnsbg %r6,%r7,110,220
.*: ec 67 92 dc e6 54 [ ]*rnsbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 54 [ ]*rnsbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38
.*: ec 67 92 1c 00 54 [ ]*rnsbgt %r6,%r7,18,28
-.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220
+.*: ec 67 6e dc e6 57 [ ]*rxsbg %r6,%r7,110,220,230
+.*: ec 67 6e dc 00 57 [ ]*rxsbg %r6,%r7,110,220
.*: ec 67 92 dc e6 57 [ ]*rxsbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 57 [ ]*rxsbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 57 [ ]*rxsbgt %r6,%r7,18,28,38
.*: ec 67 92 1c 00 57 [ ]*rxsbgt %r6,%r7,18,28
-.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220
+.*: ec 67 6e dc e6 56 [ ]*rosbg %r6,%r7,110,220,230
+.*: ec 67 6e dc 00 56 [ ]*rosbg %r6,%r7,110,220
.*: ec 67 92 dc e6 56 [ ]*rosbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 56 [ ]*rosbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 56 [ ]*rosbgt %r6,%r7,18,28,38
diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s
index 45bb8944793..a6245888c4c 100644
--- a/gas/testsuite/gas/s390/zarch-z10.s
+++ b/gas/testsuite/gas/s390/zarch-z10.s
@@ -353,20 +353,20 @@ foo:
msgfi %r6,-100000
pfd 10,5555(%r6,%r7)
pfdrl 10,.
- rnsbg %r6,%r7,210,220,230
- rnsbg %r6,%r7,210,220
+ rnsbg %r6,%r7,110,220,230
+ rnsbg %r6,%r7,110,220
rnsbg %r6,%r7,146,220,230
rnsbg %r6,%r7,146,220
rnsbgt %r6,%r7,18,28,38
rnsbgt %r6,%r7,18,28
- rxsbg %r6,%r7,210,220,230
- rxsbg %r6,%r7,210,220
+ rxsbg %r6,%r7,110,220,230
+ rxsbg %r6,%r7,110,220
rxsbg %r6,%r7,146,220,230
rxsbg %r6,%r7,146,220
rxsbgt %r6,%r7,18,28,38
rxsbgt %r6,%r7,18,28
- rosbg %r6,%r7,210,220,230
- rosbg %r6,%r7,210,220
+ rosbg %r6,%r7,110,220,230
+ rosbg %r6,%r7,110,220
rosbg %r6,%r7,146,220,230
rosbg %r6,%r7,146,220
rosbgt %r6,%r7,18,28,38
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 987004d7b07..fe0299aa4e5 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -216,15 +216,9 @@ const struct s390_operand s390_operands[] =
{ 4, 36, 0 },
#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
-#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */
- { 6, 18, 0 },
-#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */
+#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
-#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */
- { 5, 27, 0 },
-#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */
- { 6, 26, 0 },
-#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
+#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */
{ 8, 28, 0 },
@@ -288,7 +282,7 @@ unused_s390_operands_static_asserts (void)
p - pc relative
r - general purpose register
re - gpr extended operand, a valid general purpose register pair
- u - unsigned integer, 4, 6, 8, 16 or 32 bit
+ u - unsigned integer, 4, 8, 16 or 32 bit
m - mode field, 4 bit
0 - operand skipped.
The order of the letters reflects the layout of the format in
@@ -324,9 +318,9 @@ unused_s390_operands_static_asserts (void)
#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */
-#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */
-#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */
+#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */
+#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */
+#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
@@ -551,9 +545,9 @@ unused_s390_operands_static_asserts (void)
#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
-#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff }
-#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
+#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
+#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
--
2.47.0

526
SOURCES/binutils-s390-arch15-part-13.patch
Unescape View File

@ -0,0 +1,526 @@
From a98a6fa2d8ef5eb61534b07db80850dcdf07bdb4 Mon Sep 17 00:00:00 2001
From: Andreas Krebbel <krebbel@linux.ibm.com>
Date: Tue, 8 Oct 2024 12:04:31 +0200
Subject: [PATCH] s390: Add arch15 instructions
Commit: 1ff59168d0e8
opcodes/
* s390-mkopc.c (main) Accept arch15 as CPU string.
* s390-opc.txt: Add arch15 instructions.
include/
* opcode/s390.h (enum s390_opcode_cpu_val): Add
S390_OPCODE_ARCH15.
gas/
* config/tc-s390.c (s390_parse_cpu): New entry for arch15.
* doc/c-s390.texi: Document arch15 march option.
* doc/as.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run the arch15 related tests.
* testsuite/gas/s390/zarch-arch15.d: Tests for arch15
instructions.
* testsuite/gas/s390/zarch-arch15.s: Likewise.
Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com>
Reviewed-by: Jens Remus <jremus@linux.ibm.com>
---
gas/config/tc-s390.c | 2 +
gas/doc/as.texi | 2 +-
gas/doc/c-s390.texi | 7 +-
gas/testsuite/gas/s390/s390.exp | 1 +
gas/testsuite/gas/s390/zarch-arch15.d | 102 ++++++++++++++++++++++++
gas/testsuite/gas/s390/zarch-arch15.s | 96 ++++++++++++++++++++++
include/opcode/s390.h | 1 +
opcodes/s390-mkopc.c | 2 +
opcodes/s390-opc.c | 18 ++++-
opcodes/s390-opc.txt | 110 ++++++++++++++++++++++++++
10 files changed, 334 insertions(+), 7 deletions(-)
create mode 100644 gas/testsuite/gas/s390/zarch-arch15.d
create mode 100644 gas/testsuite/gas/s390/zarch-arch15.s
diff -rup binutils.orig/gas/config/tc-s390.c binutils-2.41/gas/config/tc-s390.c
--- binutils.orig/gas/config/tc-s390.c 2024-11-12 16:46:31.266202400 +0000
+++ binutils-2.41/gas/config/tc-s390.c 2024-11-12 16:46:43.847237239 +0000
@@ -294,6 +294,8 @@ s390_parse_cpu (const char *arg,
{ STRING_COMMA_LEN ("z15"), STRING_COMMA_LEN ("arch13"),
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
{ STRING_COMMA_LEN ("z16"), STRING_COMMA_LEN ("arch14"),
+ S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
+ { STRING_COMMA_LEN (""), STRING_COMMA_LEN ("arch15"),
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }
};
static struct
diff -rup binutils.orig/gas/doc/as.texi binutils-2.41/gas/doc/as.texi
--- binutils.orig/gas/doc/as.texi 2024-11-12 16:46:31.281202441 +0000
+++ binutils-2.41/gas/doc/as.texi 2024-11-12 16:46:43.850237248 +0000
@@ -1938,7 +1938,7 @@ Specify which s390 processor variant is
@samp{arch6}), @samp{z9-109}, @samp{z9-ec} (or @samp{arch7}), @samp{z10} (or
@samp{arch8}), @samp{z196} (or @samp{arch9}), @samp{zEC12} (or @samp{arch10}),
@samp{z13} (or @samp{arch11}), @samp{z14} (or @samp{arch12}), @samp{z15}
-(or @samp{arch13}), or @samp{z16} (or @samp{arch14}).
+(or @samp{arch13}), @samp{z16} (or @samp{arch14}), or @samp{arch15}.
@item -mregnames
@itemx -mno-regnames
Allow or disallow symbolic names for registers.
diff -rup binutils.orig/gas/doc/c-s390.texi binutils-2.41/gas/doc/c-s390.texi
--- binutils.orig/gas/doc/c-s390.texi 2024-11-12 16:46:31.297202486 +0000
+++ binutils-2.41/gas/doc/c-s390.texi 2024-11-12 16:46:43.851237250 +0000
@@ -18,7 +18,7 @@ and eleven chip levels. The architecture
Architecture (ESA) and the newer z/Architecture mode. The chip levels
are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
-(or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14).
+(or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or arch15.
@menu
* s390 Options:: Command-line Options.
@@ -71,8 +71,9 @@ are recognized:
@code{zEC12} (or @code{arch10}),
@code{z13} (or @code{arch11}),
@code{z14} (or @code{arch12}),
-@code{z15} (or @code{arch13}), and
-@code{z16} (or @code{arch14}).
+@code{z15} (or @code{arch13}),
+@code{z16} (or @code{arch14}), and
+@code{arch15}.
Assembling an instruction that is not supported on the target
processor results in an error message.
diff -rup binutils.orig/gas/testsuite/gas/s390/s390.exp binutils-2.41/gas/testsuite/gas/s390/s390.exp
--- binutils.orig/gas/testsuite/gas/s390/s390.exp 2024-11-12 16:46:32.163204884 +0000
+++ binutils-2.41/gas/testsuite/gas/s390/s390.exp 2024-11-12 16:46:43.851237250 +0000
@@ -33,6 +33,7 @@ if [expr [istarget "s390-*-*"] || [ista
run_dump_test "zarch-arch12" "{as -m64} {as -march=arch12}"
run_dump_test "zarch-arch13" "{as -m64} {as -march=arch13}"
run_dump_test "zarch-arch14" "{as -m64} {as -march=arch14}"
+ run_dump_test "zarch-arch15" "{as -m64} {as -march=arch15}"
run_dump_test "zarch-reloc" "{as -m64}"
run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
run_dump_test "zarch-machine" "{as -m64} {as -march=z900}"
diff --git a/gas/testsuite/gas/s390/zarch-arch15.d b/gas/testsuite/gas/s390/zarch-arch15.d
new file mode 100644
index 00000000000..955c9706b35
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-arch15.d
@@ -0,0 +1,102 @@
+#name: s390x opcode
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*: e7 f1 4d 00 87 89 [ ]*vblend %v15,%v17,%v20,%v24,13
+.*: e7 f1 40 00 87 89 [ ]*vblendb %v15,%v17,%v20,%v24
+.*: e7 f1 41 00 87 89 [ ]*vblendh %v15,%v17,%v20,%v24
+.*: e7 f1 42 00 87 89 [ ]*vblendf %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 89 [ ]*vblendg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 89 [ ]*vblendq %v15,%v17,%v20,%v24
+.*: e7 f1 40 fd 87 88 [ ]*veval %v15,%v17,%v20,%v24,253
+.*: e7 f1 00 00 d4 54 [ ]*vgem %v15,%v17,13
+.*: e7 f1 00 00 04 54 [ ]*vgemb %v15,%v17
+.*: e7 f1 00 00 14 54 [ ]*vgemh %v15,%v17
+.*: e7 f1 00 00 24 54 [ ]*vgemf %v15,%v17
+.*: e7 f1 00 00 34 54 [ ]*vgemg %v15,%v17
+.*: e7 f1 00 00 44 54 [ ]*vgemq %v15,%v17
+.*: e7 f1 00 00 34 d7 [ ]*vuphg %v15,%v17
+.*: e7 f1 00 00 34 d5 [ ]*vuplhg %v15,%v17
+.*: e7 f1 00 00 34 d6 [ ]*vuplg %v15,%v17
+.*: e7 f1 00 00 34 d4 [ ]*vupllg %v15,%v17
+.*: e7 f1 40 00 46 f2 [ ]*vavgq %v15,%v17,%v20
+.*: e7 f1 40 00 46 f0 [ ]*vavglq %v15,%v17,%v20
+.*: e7 f1 00 00 44 db [ ]*vecq %v15,%v17
+.*: e7 f1 00 00 44 d9 [ ]*veclq %v15,%v17
+.*: e7 f1 40 00 46 f8 [ ]*vceqq %v15,%v17,%v20
+.*: e7 f1 40 10 46 f8 [ ]*vceqqs %v15,%v17,%v20
+.*: e7 f1 40 00 46 fb [ ]*vchq %v15,%v17,%v20
+.*: e7 f1 40 10 46 fb [ ]*vchqs %v15,%v17,%v20
+.*: e7 f1 40 00 46 f9 [ ]*vchlq %v15,%v17,%v20
+.*: e7 f1 40 10 46 f9 [ ]*vchlqs %v15,%v17,%v20
+.*: e7 f1 00 00 44 53 [ ]*vclzq %v15,%v17
+.*: e7 f1 00 00 44 52 [ ]*vctzq %v15,%v17
+.*: e7 f1 00 00 44 de [ ]*vlcq %v15,%v17
+.*: e7 f1 00 00 44 df [ ]*vlpq %v15,%v17
+.*: e7 f1 40 00 46 ff [ ]*vmxq %v15,%v17,%v20
+.*: e7 f1 40 00 46 fd [ ]*vmxlq %v15,%v17,%v20
+.*: e7 f1 40 00 46 fe [ ]*vmnq %v15,%v17,%v20
+.*: e7 f1 40 00 46 fc [ ]*vmnlq %v15,%v17,%v20
+.*: e7 f1 43 00 87 aa [ ]*vmalg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 aa [ ]*vmalq %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ab [ ]*vmahg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 ab [ ]*vmahq %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 a9 [ ]*vmalhg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 a9 [ ]*vmalhq %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ae [ ]*vmaeg %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ac [ ]*vmaleg %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 af [ ]*vmaog %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ad [ ]*vmalog %v15,%v17,%v20,%v24
+.*: e7 f1 40 00 36 a3 [ ]*vmhg %v15,%v17,%v20
+.*: e7 f1 40 00 46 a3 [ ]*vmhq %v15,%v17,%v20
+.*: e7 f1 40 00 36 a1 [ ]*vmlhg %v15,%v17,%v20
+.*: e7 f1 40 00 46 a1 [ ]*vmlhq %v15,%v17,%v20
+.*: e7 f1 40 00 36 a2 [ ]*vmlg %v15,%v17,%v20
+.*: e7 f1 40 00 46 a2 [ ]*vmlq %v15,%v17,%v20
+.*: e7 f1 40 00 36 a6 [ ]*vmeg %v15,%v17,%v20
+.*: e7 f1 40 00 36 a4 [ ]*vmleg %v15,%v17,%v20
+.*: e7 f1 40 00 36 a7 [ ]*vmog %v15,%v17,%v20
+.*: e7 f1 40 00 36 a5 [ ]*vmlog %v15,%v17,%v20
+.*: e7 f1 40 0c d6 b2 [ ]*vd %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b2 [ ]*vdf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b2 [ ]*vdg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b2 [ ]*vdq %v15,%v17,%v20,13
+.*: e7 f1 40 0c d6 b0 [ ]*vdl %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b0 [ ]*vdlf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b0 [ ]*vdlg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b0 [ ]*vdlq %v15,%v17,%v20,13
+.*: e7 f1 40 0c d6 b3 [ ]*vr %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b3 [ ]*vrf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b3 [ ]*vrg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b3 [ ]*vrq %v15,%v17,%v20,13
+.*: e7 f1 40 0c d6 b1 [ ]*vrl %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b1 [ ]*vrlf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b1 [ ]*vrlg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b1 [ ]*vrlq %v15,%v17,%v20,13
+.*: b9 68 00 69 [ ]*clzg %r6,%r9
+.*: b9 69 00 69 [ ]*ctzg %r6,%r9
+.*: e3 69 b8 f0 fd 60 [ ]*lxab %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 62 [ ]*lxah %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 64 [ ]*lxaf %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 66 [ ]*lxag %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 68 [ ]*lxaq %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 61 [ ]*llxab %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 63 [ ]*llxah %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 65 [ ]*llxaf %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 67 [ ]*llxag %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 69 [ ]*llxaq %r6,-10000\(%r9,%r11\)
+.*: b9 6c b0 69 [ ]*bextg %r6,%r9,%r11
+.*: b9 6d b0 69 [ ]*bdepg %r6,%r9,%r11
+.*: b9 3e 00 69 [ ]*kimd %r6,%r9
+.*: b9 3e d0 69 [ ]*kimd %r6,%r9,13
+.*: b9 3f 00 69 [ ]*klmd %r6,%r9
+.*: b9 3f d0 69 [ ]*klmd %r6,%r9,13
+.*: e6 f1 00 d0 04 4e [ ]*vcvbq %v15,%v17,13
+.*: e6 f1 00 cf d4 4a [ ]*vcvdq %v15,%v17,253,12
+.*: e6 0f 00 00 00 5f [ ]*vtp %v15
+.*: e6 0f 0f ff d0 5f [ ]*vtp %v15,65533
+.*: e6 0f 1f ff d2 7f [ ]*vtz %v15,%v17,65533
diff --git a/gas/testsuite/gas/s390/zarch-arch15.s b/gas/testsuite/gas/s390/zarch-arch15.s
new file mode 100644
index 00000000000..43be9d46a48
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-arch15.s
@@ -0,0 +1,96 @@
+.text
+foo:
+ vblend %v15,%v17,%v20,%v24,13
+ vblendb %v15,%v17,%v20,%v24
+ vblendh %v15,%v17,%v20,%v24
+ vblendf %v15,%v17,%v20,%v24
+ vblendg %v15,%v17,%v20,%v24
+ vblendq %v15,%v17,%v20,%v24
+ veval %v15,%v17,%v20,%v24,253
+ vgem %v15,%v17,13
+ vgemb %v15,%v17
+ vgemh %v15,%v17
+ vgemf %v15,%v17
+ vgemg %v15,%v17
+ vgemq %v15,%v17
+ vuphg %v15,%v17
+ vuplhg %v15,%v17
+ vuplg %v15,%v17
+ vupllg %v15,%v17
+ vavgq %v15,%v17,%v20
+ vavglq %v15,%v17,%v20
+ vecq %v15,%v17
+ veclq %v15,%v17
+ vceqq %v15,%v17,%v20
+ vceqqs %v15,%v17,%v20
+ vchq %v15,%v17,%v20
+ vchqs %v15,%v17,%v20
+ vchlq %v15,%v17,%v20
+ vchlqs %v15,%v17,%v20
+ vclzq %v15,%v17
+ vctzq %v15,%v17
+ vlcq %v15,%v17
+ vlpq %v15,%v17
+ vmxq %v15,%v17,%v20
+ vmxlq %v15,%v17,%v20
+ vmnq %v15,%v17,%v20
+ vmnlq %v15,%v17,%v20
+ vmalg %v15,%v17,%v20,%v24
+ vmalq %v15,%v17,%v20,%v24
+ vmahg %v15,%v17,%v20,%v24
+ vmahq %v15,%v17,%v20,%v24
+ vmalhg %v15,%v17,%v20,%v24
+ vmalhq %v15,%v17,%v20,%v24
+ vmaeg %v15,%v17,%v20,%v24
+ vmaleg %v15,%v17,%v20,%v24
+ vmaog %v15,%v17,%v20,%v24
+ vmalog %v15,%v17,%v20,%v24
+ vmhg %v15,%v17,%v20
+ vmhq %v15,%v17,%v20
+ vmlhg %v15,%v17,%v20
+ vmlhq %v15,%v17,%v20
+ vmlg %v15,%v17,%v20
+ vmlq %v15,%v17,%v20
+ vmeg %v15,%v17,%v20
+ vmleg %v15,%v17,%v20
+ vmog %v15,%v17,%v20
+ vmlog %v15,%v17,%v20
+ vd %v15,%v17,%v20,13,12
+ vdf %v15,%v17,%v20,13
+ vdg %v15,%v17,%v20,13
+ vdq %v15,%v17,%v20,13
+ vdl %v15,%v17,%v20,13,12
+ vdlf %v15,%v17,%v20,13
+ vdlg %v15,%v17,%v20,13
+ vdlq %v15,%v17,%v20,13
+ vr %v15,%v17,%v20,13,12
+ vrf %v15,%v17,%v20,13
+ vrg %v15,%v17,%v20,13
+ vrq %v15,%v17,%v20,13
+ vrl %v15,%v17,%v20,13,12
+ vrlf %v15,%v17,%v20,13
+ vrlg %v15,%v17,%v20,13
+ vrlq %v15,%v17,%v20,13
+ clzg %r6,%r9
+ ctzg %r6,%r9
+ lxab %r6,-10000(%r9,%r11)
+ lxah %r6,-10000(%r9,%r11)
+ lxaf %r6,-10000(%r9,%r11)
+ lxag %r6,-10000(%r9,%r11)
+ lxaq %r6,-10000(%r9,%r11)
+ llxab %r6,-10000(%r9,%r11)
+ llxah %r6,-10000(%r9,%r11)
+ llxaf %r6,-10000(%r9,%r11)
+ llxag %r6,-10000(%r9,%r11)
+ llxaq %r6,-10000(%r9,%r11)
+ bextg %r6,%r9,%r11
+ bdepg %r6,%r9,%r11
+ kimd %r6,%r9
+ kimd %r6,%r9,13
+ klmd %r6,%r9
+ klmd %r6,%r9,13
+ vcvbq %v15,%v17,13
+ vcvdq %v15,%v17,253,12
+ vtp %v15
+ vtp %v15,65533
+ vtz %v15,%v17,65533
diff -rup binutils.orig/include/opcode/s390.h binutils-2.41/include/opcode/s390.h
--- binutils.orig/include/opcode/s390.h 2024-11-12 16:46:32.458205701 +0000
+++ binutils-2.41/include/opcode/s390.h 2024-11-12 16:46:43.852237253 +0000
@@ -45,6 +45,7 @@ enum s390_opcode_cpu_val
S390_OPCODE_ARCH12,
S390_OPCODE_ARCH13,
S390_OPCODE_ARCH14,
+ S390_OPCODE_ARCH15,
S390_OPCODE_MAXCPU
};
diff -rup binutils.orig/opcodes/s390-mkopc.c binutils-2.41/opcodes/s390-mkopc.c
--- binutils.orig/opcodes/s390-mkopc.c 2024-11-12 16:46:33.158207639 +0000
+++ binutils-2.41/opcodes/s390-mkopc.c 2024-11-12 16:46:43.852237253 +0000
@@ -384,6 +384,8 @@ main (void)
else if (strcmp (cpu_string, "z16") == 0
|| strcmp (cpu_string, "arch14") == 0)
min_cpu = S390_OPCODE_ARCH14;
+ else if (strcmp (cpu_string, "arch15") == 0)
+ min_cpu = S390_OPCODE_ARCH15;
else {
fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
exit (1);
diff -rup binutils.orig/opcodes/s390-opc.c binutils-2.41/opcodes/s390-opc.c
--- binutils.orig/opcodes/s390-opc.c 2024-11-12 16:46:33.194207739 +0000
+++ binutils-2.41/opcodes/s390-opc.c 2024-11-12 16:46:43.853237256 +0000
@@ -228,7 +228,9 @@ const struct s390_operand s390_operands[
{ 12, 16, 0 },
#define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */
{ 16, 16, 0 },
-#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */
+#define U16_20 (U16_16 + 1) /* 16 bit unsigned value starting at 20 */
+ { 16, 20, 0 },
+#define U16_32 (U16_20 + 1) /* 16 bit unsigned value starting at 32 */
{ 16, 32, 0 },
#define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */
{ 32, 16, 0 },
@@ -484,6 +486,8 @@ unused_s390_operands_static_asserts (voi
#define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */
#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */
#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */
+#define INSTR_VRI_VV0UU 6, { V_8,V_12,U8_28,U4_24,0,0 } /* e.g. vcvdq */
+#define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */
#define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */
#define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */
#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */
@@ -494,10 +498,10 @@ unused_s390_operands_static_asserts (voi
#define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */
#define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */
#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */
-#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */
#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */
#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */
#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */
+#define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */
#define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/
#define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/
#define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/
@@ -523,6 +527,9 @@ unused_s390_operands_static_asserts (voi
#define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */
#define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */
#define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */
+#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */
+#define INSTR_VRR_0V0U 6, { V_12,U16_20,0,0,0,0 } /* e.g. vtp */
+#define INSTR_VRR_0VVU 6, { V_12,V_16,U16_20,0,0,0 } /* e.g. vtz */
#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */
#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */
#define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */
@@ -711,6 +718,8 @@ unused_s390_operands_static_asserts (voi
#define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
+#define MASK_VRI_VV0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
+#define MASK_VRI_VVV0UV { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff }
#define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
#define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff }
#define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -721,10 +730,10 @@ unused_s390_operands_static_asserts (voi
#define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
-#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff }
#define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff }
#define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff }
#define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff }
+#define MASK_VRR_VVV0U02 { 0xff, 0x00, 0x0f, 0xf0, 0xf0, 0xff }
#define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff }
#define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff }
#define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff }
@@ -750,6 +759,9 @@ unused_s390_operands_static_asserts (voi
#define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
#define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff }
#define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff }
+#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff }
+#define MASK_VRR_0V0U { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff }
+#define MASK_VRR_0VVU { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff }
#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
#define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff }
diff -rup binutils.orig/opcodes/s390-opc.txt binutils-2.41/opcodes/s390-opc.txt
--- binutils.orig/opcodes/s390-opc.txt 2024-11-12 16:46:33.194207739 +0000
+++ binutils-2.41/opcodes/s390-opc.txt 2024-11-12 16:46:43.854237258 +0000
@@ -2072,3 +2072,113 @@ b201 stbear S_RD "store bear" arch14 zar
# Processor-Activity-Instrumentation Facility
b28f qpaci S_RD "query processor activity counter information" arch14 zarch
+
+
+# arch15 instructions
+
+e70000000089 vblend VRR_VVVU0V " " arch15 zarch
+e70000000089 vblendb VRR_VVV0V " " arch15 zarch
+e70001000089 vblendh VRR_VVV0V " " arch15 zarch
+e70002000089 vblendf VRR_VVV0V " " arch15 zarch
+e70003000089 vblendg VRR_VVV0V " " arch15 zarch
+e70004000089 vblendq VRR_VVV0V " " arch15 zarch
+
+e70000000088 veval VRI_VVV0UV " " arch15 zarch
+
+e70000000054 vgem VRR_VV0U " " arch15 zarch
+e70000000054 vgemb VRR_VV " " arch15 zarch
+e70000001054 vgemh VRR_VV " " arch15 zarch
+e70000002054 vgemf VRR_VV " " arch15 zarch
+e70000003054 vgemg VRR_VV " " arch15 zarch
+e70000004054 vgemq VRR_VV " " arch15 zarch
+
+e700000030d7 vuphg VRR_VV " " arch15 zarch
+e700000030d5 vuplhg VRR_VV " " arch15 zarch
+e700000030d6 vuplg VRR_VV " " arch15 zarch
+e700000030d4 vupllg VRR_VV " " arch15 zarch
+
+e700000040f2 vavgq VRR_VVV " " arch15 zarch
+e700000040f0 vavglq VRR_VVV " " arch15 zarch
+e700000040db vecq VRR_VV " " arch15 zarch
+e700000040d9 veclq VRR_VV " " arch15 zarch
+e700000040f8 vceqq VRR_VVV " " arch15 zarch
+e700001040f8 vceqqs VRR_VVV " " arch15 zarch
+e700000040fb vchq VRR_VVV " " arch15 zarch
+e700001040fb vchqs VRR_VVV " " arch15 zarch
+e700000040f9 vchlq VRR_VVV " " arch15 zarch
+e700001040f9 vchlqs VRR_VVV " " arch15 zarch
+e70000004053 vclzq VRR_VV " " arch15 zarch
+e70000004052 vctzq VRR_VV " " arch15 zarch
+e700000040de vlcq VRR_VV " " arch15 zarch
+e700000040df vlpq VRR_VV " " arch15 zarch
+e700000040ff vmxq VRR_VVV " " arch15 zarch
+e700000040fd vmxlq VRR_VVV " " arch15 zarch
+e700000040fe vmnq VRR_VVV " " arch15 zarch
+e700000040fc vmnlq VRR_VVV " " arch15 zarch
+e700030000aa vmalg VRR_VVV0V " " arch15 zarch
+e700040000aa vmalq VRR_VVV0V " " arch15 zarch
+e700030000ab vmahg VRR_VVV0V " " arch15 zarch
+e700040000ab vmahq VRR_VVV0V " " arch15 zarch
+e700030000a9 vmalhg VRR_VVV0V " " arch15 zarch
+e700040000a9 vmalhq VRR_VVV0V " " arch15 zarch
+e700030000ae vmaeg VRR_VVV0V " " arch15 zarch
+e700030000ac vmaleg VRR_VVV0V " " arch15 zarch
+e700030000af vmaog VRR_VVV0V " " arch15 zarch
+e700030000ad vmalog VRR_VVV0V " " arch15 zarch
+e700000030a3 vmhg VRR_VVV " " arch15 zarch
+e700000040a3 vmhq VRR_VVV " " arch15 zarch
+e700000030a1 vmlhg VRR_VVV " " arch15 zarch
+e700000040a1 vmlhq VRR_VVV " " arch15 zarch
+e700000030a2 vmlg VRR_VVV " " arch15 zarch
+e700000040a2 vmlq VRR_VVV " " arch15 zarch
+e700000030a6 vmeg VRR_VVV " " arch15 zarch
+e700000030a4 vmleg VRR_VVV " " arch15 zarch
+e700000030a7 vmog VRR_VVV " " arch15 zarch
+e700000030a5 vmlog VRR_VVV " " arch15 zarch
+
+e700000000b2 vd VRR_VVV0UU " " arch15 zarch
+e700000020b2 vdf VRR_VVV0U02 " " arch15 zarch
+e700000030b2 vdg VRR_VVV0U02 " " arch15 zarch
+e700000040b2 vdq VRR_VVV0U02 " " arch15 zarch
+
+e700000000b0 vdl VRR_VVV0UU " " arch15 zarch
+e700000020b0 vdlf VRR_VVV0U02 " " arch15 zarch
+e700000030b0 vdlg VRR_VVV0U02 " " arch15 zarch
+e700000040b0 vdlq VRR_VVV0U02 " " arch15 zarch
+
+e700000000b3 vr VRR_VVV0UU " " arch15 zarch
+e700000020b3 vrf VRR_VVV0U02 " " arch15 zarch
+e700000030b3 vrg VRR_VVV0U02 " " arch15 zarch
+e700000040b3 vrq VRR_VVV0U02 " " arch15 zarch
+
+e700000000b1 vrl VRR_VVV0UU " " arch15 zarch
+e700000020b1 vrlf VRR_VVV0U02 " " arch15 zarch
+e700000030b1 vrlg VRR_VVV0U02 " " arch15 zarch
+e700000040b1 vrlq VRR_VVV0U02 " " arch15 zarch
+
+b968 clzg RRE_RR " " arch15 zarch
+b969 ctzg RRE_RR " " arch15 zarch
+
+e30000000060 lxab RXY_RRRD " " arch15 zarch
+e30000000062 lxah RXY_RRRD " " arch15 zarch
+e30000000064 lxaf RXY_RRRD " " arch15 zarch
+e30000000066 lxag RXY_RRRD " " arch15 zarch
+e30000000068 lxaq RXY_RRRD " " arch15 zarch
+
+e30000000061 llxab RXY_RRRD " " arch15 zarch
+e30000000063 llxah RXY_RRRD " " arch15 zarch
+e30000000065 llxaf RXY_RRRD " " arch15 zarch
+e30000000067 llxag RXY_RRRD " " arch15 zarch
+e30000000069 llxaq RXY_RRRD " " arch15 zarch
+
+b96c bextg RRF_R0RR2 " " arch15 zarch
+b96d bdepg RRF_R0RR2 " " arch15 zarch
+
+b93e kimd RRF_U0RR " " arch15 zarch optparm
+b93f klmd RRF_U0RR " " arch15 zarch optparm
+
+e6000000004e vcvbq VRR_VV0U2 " " arch15 zarch
+e6000000004a vcvdq VRI_VV0UU " " arch15 zarch
+
+e6000000005f vtp VRR_0V0U " " arch15 zarch optparm
+e6000000007f vtz VRR_0VVU " " arch15 zarch

245
SOURCES/binutils-s390-arch15-part-14.patch
Unescape View File

@ -0,0 +1,245 @@
From 76c1ece3a59b26b3744136455eeca0dcf07d8f9d Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Mon, 18 Nov 2024 10:42:21 +0100
Subject: [PATCH] s390: Add arch15 instruction names
opcodes/
* s390-opc.txt: Add arch15 instruction names.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit b0588b2173bf9aeff9eadc0cc024c4c69e69114d)
---
opcodes/s390-opc.txt | 220 ++++++++++++++++++++++---------------------
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 089fd197b0c..c01face4eb6 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2076,109 +2076,117 @@ b28f qpaci S_RD "query processor activity counter information" arch14 zarch
# arch15 instructions
-e70000000089 vblend VRR_VVVU0V " " arch15 zarch
-e70000000089 vblendb VRR_VVV0V " " arch15 zarch
-e70001000089 vblendh VRR_VVV0V " " arch15 zarch
-e70002000089 vblendf VRR_VVV0V " " arch15 zarch
-e70003000089 vblendg VRR_VVV0V " " arch15 zarch
-e70004000089 vblendq VRR_VVV0V " " arch15 zarch
-
-e70000000088 veval VRI_VVV0UV " " arch15 zarch
-
-e70000000054 vgem VRR_VV0U " " arch15 zarch
-e70000000054 vgemb VRR_VV " " arch15 zarch
-e70000001054 vgemh VRR_VV " " arch15 zarch
-e70000002054 vgemf VRR_VV " " arch15 zarch
-e70000003054 vgemg VRR_VV " " arch15 zarch
-e70000004054 vgemq VRR_VV " " arch15 zarch
-
-e700000030d7 vuphg VRR_VV " " arch15 zarch
-e700000030d5 vuplhg VRR_VV " " arch15 zarch
-e700000030d6 vuplg VRR_VV " " arch15 zarch
-e700000030d4 vupllg VRR_VV " " arch15 zarch
-
-e700000040f2 vavgq VRR_VVV " " arch15 zarch
-e700000040f0 vavglq VRR_VVV " " arch15 zarch
-e700000040db vecq VRR_VV " " arch15 zarch
-e700000040d9 veclq VRR_VV " " arch15 zarch
-e700000040f8 vceqq VRR_VVV " " arch15 zarch
-e700001040f8 vceqqs VRR_VVV " " arch15 zarch
-e700000040fb vchq VRR_VVV " " arch15 zarch
-e700001040fb vchqs VRR_VVV " " arch15 zarch
-e700000040f9 vchlq VRR_VVV " " arch15 zarch
-e700001040f9 vchlqs VRR_VVV " " arch15 zarch
-e70000004053 vclzq VRR_VV " " arch15 zarch
-e70000004052 vctzq VRR_VV " " arch15 zarch
-e700000040de vlcq VRR_VV " " arch15 zarch
-e700000040df vlpq VRR_VV " " arch15 zarch
-e700000040ff vmxq VRR_VVV " " arch15 zarch
-e700000040fd vmxlq VRR_VVV " " arch15 zarch
-e700000040fe vmnq VRR_VVV " " arch15 zarch
-e700000040fc vmnlq VRR_VVV " " arch15 zarch
-e700030000aa vmalg VRR_VVV0V " " arch15 zarch
-e700040000aa vmalq VRR_VVV0V " " arch15 zarch
-e700030000ab vmahg VRR_VVV0V " " arch15 zarch
-e700040000ab vmahq VRR_VVV0V " " arch15 zarch
-e700030000a9 vmalhg VRR_VVV0V " " arch15 zarch
-e700040000a9 vmalhq VRR_VVV0V " " arch15 zarch
-e700030000ae vmaeg VRR_VVV0V " " arch15 zarch
-e700030000ac vmaleg VRR_VVV0V " " arch15 zarch
-e700030000af vmaog VRR_VVV0V " " arch15 zarch
-e700030000ad vmalog VRR_VVV0V " " arch15 zarch
-e700000030a3 vmhg VRR_VVV " " arch15 zarch
-e700000040a3 vmhq VRR_VVV " " arch15 zarch
-e700000030a1 vmlhg VRR_VVV " " arch15 zarch
-e700000040a1 vmlhq VRR_VVV " " arch15 zarch
-e700000030a2 vmlg VRR_VVV " " arch15 zarch
-e700000040a2 vmlq VRR_VVV " " arch15 zarch
-e700000030a6 vmeg VRR_VVV " " arch15 zarch
-e700000030a4 vmleg VRR_VVV " " arch15 zarch
-e700000030a7 vmog VRR_VVV " " arch15 zarch
-e700000030a5 vmlog VRR_VVV " " arch15 zarch
-
-e700000000b2 vd VRR_VVV0UU " " arch15 zarch
-e700000020b2 vdf VRR_VVV0U02 " " arch15 zarch
-e700000030b2 vdg VRR_VVV0U02 " " arch15 zarch
-e700000040b2 vdq VRR_VVV0U02 " " arch15 zarch
-
-e700000000b0 vdl VRR_VVV0UU " " arch15 zarch
-e700000020b0 vdlf VRR_VVV0U02 " " arch15 zarch
-e700000030b0 vdlg VRR_VVV0U02 " " arch15 zarch
-e700000040b0 vdlq VRR_VVV0U02 " " arch15 zarch
-
-e700000000b3 vr VRR_VVV0UU " " arch15 zarch
-e700000020b3 vrf VRR_VVV0U02 " " arch15 zarch
-e700000030b3 vrg VRR_VVV0U02 " " arch15 zarch
-e700000040b3 vrq VRR_VVV0U02 " " arch15 zarch
-
-e700000000b1 vrl VRR_VVV0UU " " arch15 zarch
-e700000020b1 vrlf VRR_VVV0U02 " " arch15 zarch
-e700000030b1 vrlg VRR_VVV0U02 " " arch15 zarch
-e700000040b1 vrlq VRR_VVV0U02 " " arch15 zarch
-
-b968 clzg RRE_RR " " arch15 zarch
-b969 ctzg RRE_RR " " arch15 zarch
-
-e30000000060 lxab RXY_RRRD " " arch15 zarch
-e30000000062 lxah RXY_RRRD " " arch15 zarch
-e30000000064 lxaf RXY_RRRD " " arch15 zarch
-e30000000066 lxag RXY_RRRD " " arch15 zarch
-e30000000068 lxaq RXY_RRRD " " arch15 zarch
-
-e30000000061 llxab RXY_RRRD " " arch15 zarch
-e30000000063 llxah RXY_RRRD " " arch15 zarch
-e30000000065 llxaf RXY_RRRD " " arch15 zarch
-e30000000067 llxag RXY_RRRD " " arch15 zarch
-e30000000069 llxaq RXY_RRRD " " arch15 zarch
-
-b96c bextg RRF_R0RR2 " " arch15 zarch
-b96d bdepg RRF_R0RR2 " " arch15 zarch
-
-b93e kimd RRF_U0RR " " arch15 zarch optparm
-b93f klmd RRF_U0RR " " arch15 zarch optparm
-
-e6000000004e vcvbq VRR_VV0U2 " " arch15 zarch
-e6000000004a vcvdq VRI_VV0UU " " arch15 zarch
-
-e6000000005f vtp VRR_0V0U " " arch15 zarch optparm
-e6000000007f vtz VRR_0VVU " " arch15 zarch
+# Vector-Enhancements Facility 3
+
+e70000000089 vblend VRR_VVVU0V "vector blend" arch15 zarch
+e70000000089 vblendb VRR_VVV0V "vector blend byte" arch15 zarch
+e70001000089 vblendh VRR_VVV0V "vector blend halfword" arch15 zarch
+e70002000089 vblendf VRR_VVV0V "vector blend word" arch15 zarch
+e70003000089 vblendg VRR_VVV0V "vector blend doubleword" arch15 zarch
+e70004000089 vblendq VRR_VVV0V "vector blend quadword" arch15 zarch
+
+e70000000088 veval VRI_VVV0UV "vector evaluate" arch15 zarch
+
+e70000000054 vgem VRR_VV0U "vector generate element masks" arch15 zarch
+e70000000054 vgemb VRR_VV "vector generate element masks byte" arch15 zarch
+e70000001054 vgemh VRR_VV "vector generate element masks halfword" arch15 zarch
+e70000002054 vgemf VRR_VV "vector generate element masks word" arch15 zarch
+e70000003054 vgemg VRR_VV "vector generate element masks doubleword" arch15 zarch
+e70000004054 vgemq VRR_VV "vector generate element masks quadword" arch15 zarch
+
+e700000030d7 vuphg VRR_VV "vector unpack high doubleword" arch15 zarch
+e700000030d5 vuplhg VRR_VV "vector unpack logical high doubleword" arch15 zarch
+e700000030d6 vuplg VRR_VV "vector unpack low doubleword" arch15 zarch
+e700000030d4 vupllg VRR_VV "vector unpack logical low doubleword" arch15 zarch
+
+e700000040f2 vavgq VRR_VVV "vector average quadword" arch15 zarch
+e700000040f0 vavglq VRR_VVV "vector average logical quadword" arch15 zarch
+e700000040db vecq VRR_VV "vector element compare quadword" arch15 zarch
+e700000040d9 veclq VRR_VV "vector element compare logical quadword" arch15 zarch
+e700000040f8 vceqq VRR_VVV "vector compare equal quadword" arch15 zarch
+e700001040f8 vceqqs VRR_VVV "vector compare equal quadword" arch15 zarch
+e700000040fb vchq VRR_VVV "vector compare high quadword" arch15 zarch
+e700001040fb vchqs VRR_VVV "vector compare high quadword" arch15 zarch
+e700000040f9 vchlq VRR_VVV "vector compare high logical quadword" arch15 zarch
+e700001040f9 vchlqs VRR_VVV "vector compare high logical quadword" arch15 zarch
+e70000004053 vclzq VRR_VV "vector count leading zeros quadword" arch15 zarch
+e70000004052 vctzq VRR_VV "vector count trailing zeros quadword" arch15 zarch
+e700000040de vlcq VRR_VV "vector load complement quadword" arch15 zarch
+e700000040df vlpq VRR_VV "vector load positive quadword" arch15 zarch
+e700000040ff vmxq VRR_VVV "vector maximum quadword" arch15 zarch
+e700000040fd vmxlq VRR_VVV "vector maximum logical quadword" arch15 zarch
+e700000040fe vmnq VRR_VVV "vector minimum quadword" arch15 zarch
+e700000040fc vmnlq VRR_VVV "vector minimum logical quadword" arch15 zarch
+e700030000aa vmalg VRR_VVV0V "vector multiply and add low doubleword" arch15 zarch
+e700040000aa vmalq VRR_VVV0V "vector multiply and add low quadword" arch15 zarch
+e700030000ab vmahg VRR_VVV0V "vector multiply and add high doubleword" arch15 zarch
+e700040000ab vmahq VRR_VVV0V "vector multiply and add high quadword" arch15 zarch
+e700030000a9 vmalhg VRR_VVV0V "vector multiply and add logical high doubleword" arch15 zarch
+e700040000a9 vmalhq VRR_VVV0V "vector multiply and add logical high quadword" arch15 zarch
+e700030000ae vmaeg VRR_VVV0V "vector multiply and add even doubleword" arch15 zarch
+e700030000ac vmaleg VRR_VVV0V "vector multiply and add logical even doubleword" arch15 zarch
+e700030000af vmaog VRR_VVV0V "vector multiply and add odd doubleword" arch15 zarch
+e700030000ad vmalog VRR_VVV0V "vector multiply and add logical odd doubleword" arch15 zarch
+e700000030a3 vmhg VRR_VVV "vector multiply high doubleword" arch15 zarch
+e700000040a3 vmhq VRR_VVV "vector multiply high quadword" arch15 zarch
+e700000030a1 vmlhg VRR_VVV "vector multiply logical high doubleword" arch15 zarch
+e700000040a1 vmlhq VRR_VVV "vector multiply logical high quadword" arch15 zarch
+e700000030a2 vmlg VRR_VVV "vector multiply low doubleword" arch15 zarch
+e700000040a2 vmlq VRR_VVV "vector multiply low quadword" arch15 zarch
+e700000030a6 vmeg VRR_VVV "vector multiply even doubleword" arch15 zarch
+e700000030a4 vmleg VRR_VVV "vector multiply logical even doubleword" arch15 zarch
+e700000030a7 vmog VRR_VVV "vector multiply odd doubleword" arch15 zarch
+e700000030a5 vmlog VRR_VVV "vector multiply logical odd doubleword" arch15 zarch
+
+e700000000b2 vd VRR_VVV0UU "vector divide" arch15 zarch
+e700000020b2 vdf VRR_VVV0U02 "vector divide word" arch15 zarch
+e700000030b2 vdg VRR_VVV0U02 "vector divide doubleword" arch15 zarch
+e700000040b2 vdq VRR_VVV0U02 "vector divide quadword" arch15 zarch
+
+e700000000b0 vdl VRR_VVV0UU "vector divide logical" arch15 zarch
+e700000020b0 vdlf VRR_VVV0U02 "vector divide logical word" arch15 zarch
+e700000030b0 vdlg VRR_VVV0U02 "vector divide logical doubleword" arch15 zarch
+e700000040b0 vdlq VRR_VVV0U02 "vector divide logical quadword" arch15 zarch
+
+e700000000b3 vr VRR_VVV0UU "vector remainder" arch15 zarch
+e700000020b3 vrf VRR_VVV0U02 "vector remainder word" arch15 zarch
+e700000030b3 vrg VRR_VVV0U02 "vector remainder doubleword" arch15 zarch
+e700000040b3 vrq VRR_VVV0U02 "vector remainder quadword" arch15 zarch
+
+e700000000b1 vrl VRR_VVV0UU "vector remainder logical" arch15 zarch
+e700000020b1 vrlf VRR_VVV0U02 "vector remainder logical word" arch15 zarch
+e700000030b1 vrlg VRR_VVV0U02 "vector remainder logical doubleword" arch15 zarch
+e700000040b1 vrlq VRR_VVV0U02 "vector remainder logical quadword" arch15 zarch
+
+# Miscellaneous-Instruction-Extensions Facility 4
+
+b968 clzg RRE_RR "count leading zeros" arch15 zarch
+b969 ctzg RRE_RR "count trailing zeros" arch15 zarch
+
+e30000000060 lxab RXY_RRRD "load indexed address (shift left 0)" arch15 zarch
+e30000000062 lxah RXY_RRRD "load indexed address (shift left 1)" arch15 zarch
+e30000000064 lxaf RXY_RRRD "load indexed address (shift left 2)" arch15 zarch
+e30000000066 lxag RXY_RRRD "load indexed address (shift left 3)" arch15 zarch
+e30000000068 lxaq RXY_RRRD "load indexed address (shift left 4)" arch15 zarch
+
+e30000000061 llxab RXY_RRRD "load logical indexed address (shift left 0)" arch15 zarch
+e30000000063 llxah RXY_RRRD "load logical indexed address (shift left 1)" arch15 zarch
+e30000000065 llxaf RXY_RRRD "load logical indexed address (shift left 2)" arch15 zarch
+e30000000067 llxag RXY_RRRD "load logical indexed address (shift left 3)" arch15 zarch
+e30000000069 llxaq RXY_RRRD "load logical indexed address (shift left 4)" arch15 zarch
+
+b96c bextg RRF_R0RR2 "bit extract" arch15 zarch
+b96d bdepg RRF_R0RR2 "bit deposit" arch15 zarch
+
+# Message-Security-Assist Extension 12
+
+b93e kimd RRF_U0RR "compute intermediate message digest" arch15 zarch optparm
+b93f klmd RRF_U0RR "compute last message digest" arch15 zarch optparm
+
+# Vector-Packed-Decimal-Enhancement Facility 3
+
+e6000000004e vcvbq VRR_VV0U2 "vector convert to binary 128 bit" arch15 zarch
+e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch
+
+e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm
+e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch
--
2.47.0

88
SOURCES/binutils-s390-arch15-part-15.patch
Unescape View File

@ -0,0 +1,88 @@
From 94c65b893a7aea968b06a3e97eef466abc49fbe5 Mon Sep 17 00:00:00 2001
From: Jens Remus <jremus@linux.ibm.com>
Date: Mon, 18 Nov 2024 10:42:21 +0100
Subject: [PATCH] s390: Add arch15 Concurrent-Functions Facility insns
opcodes/
* s390-opc.txt: Add arch15 Concurrent-Functions Facility
instructions.
* s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF
instruction format variant.
gas/testsuite/
* gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions
Facility instructions.
* gas/s390/zarch-arch15.s: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit 76445f36a2f9e41b1744d0327e7ec243cb7fac12)
---
gas/testsuite/gas/s390/zarch-arch15.d | 4 ++++
gas/testsuite/gas/s390/zarch-arch15.s | 4 ++++
opcodes/s390-opc.c | 2 ++
opcodes/s390-opc.txt | 8 ++++++++
4 files changed, 18 insertions(+)
diff --git a/gas/testsuite/gas/s390/zarch-arch15.d b/gas/testsuite/gas/s390/zarch-arch15.d
index 955c9706b35..9cd99b7a698 100644
--- a/gas/testsuite/gas/s390/zarch-arch15.d
+++ b/gas/testsuite/gas/s390/zarch-arch15.d
@@ -100,3 +100,7 @@ Disassembly of section .text:
.*: e6 0f 00 00 00 5f [ ]*vtp %v15
.*: e6 0f 0f ff d0 5f [ ]*vtp %v15,65533
.*: e6 0f 1f ff d2 7f [ ]*vtz %v15,%v17,65533
+.*: c8 36 10 0a 20 14 [ ]*cal %r3,10\(%r1\),20\(%r2\)
+.*: c8 37 10 0a 20 14 [ ]*calg %r3,10\(%r1\),20\(%r2\)
+.*: c8 3f 10 0a 20 14 [ ]*calgf %r3,10\(%r1\),20\(%r2\)
+.*: eb 13 28 f0 fd 16 [ ]*pfcr %r1,%r3,-10000\(%r2\)
diff --git a/gas/testsuite/gas/s390/zarch-arch15.s b/gas/testsuite/gas/s390/zarch-arch15.s
index 43be9d46a48..d9b89652fcb 100644
--- a/gas/testsuite/gas/s390/zarch-arch15.s
+++ b/gas/testsuite/gas/s390/zarch-arch15.s
@@ -94,3 +94,7 @@ foo:
vtp %v15
vtp %v15,65533
vtz %v15,%v17,65533
+ cal %r3,10(%r1),20(%r2)
+ calg %r3,10(%r1),20(%r2)
+ calgf %r3,10(%r1),20(%r2)
+ pfcr %r1,%r3,-10000(%r2)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 1964feb639d..1e26fda8a31 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -466,6 +466,7 @@ unused_s390_operands_static_asserts (void)
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */
#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */
@@ -698,6 +699,7 @@ unused_s390_operands_static_asserts (void)
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index c01face4eb6..ab00a8cd408 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2190,3 +2190,11 @@ e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch
e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm
e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch
+
+# Concurrent-Functions Facility
+
+c806 cal SSF_RRDRD2 "compare and load 32" arch15 zarch
+c807 calg SSF_RRDRD2 "compare and load 64" arch15 zarch
+c80f calgf SSF_RRDRD2 "compare and load 64<32" arch15 zarch
+
+eb0000000016 pfcr RSY_RRRD "perform functions with concurrent results" arch15 zarch
--
2.47.0

15
SOURCES/binutils-testsuite-fixes.patch
Unescape View File

@ -984,3 +984,18 @@ diff -rup binutils.orig/ld/testsuite/ld-powerpc/tls32no.g binutils-2.41/ld/tests
- 1810154 (0+01 f+8020 f+9030 0+01|010+ 2080f+ 3090f+ 010+) .*
- 1810164 0+ 0+ 0+ 0+0 .*
+#pass
--- binutils.orig/ld/testsuite/ld-plugin/lto.exp 2024-11-12 19:07:17.085947672 +0000
+++ binutils-2.41/ld/testsuite/ld-plugin/lto.exp 2024-11-12 19:09:02.417201301 +0000
@@ -638,12 +638,6 @@ set lto_run_tests [list \
[list "Run pr20276" \
"-O2 -flto tmpdir/pr20276a.o tmpdir/pr20276b.o" "" \
{dummy.c} "pr20276" "pass.out" "-flto -O2" "c"] \
- [list "Run pr20267a" \
- "-O2 -flto -fcommon tmpdir/pr20267a.o tmpdir/libpr20267a.a" "" \
- {dummy.c} "pr20267a" "pass.out" "-flto -O2 -fcommon" "c"] \
- [list "Run pr20267b" \
- "-O2 -flto -fcommon tmpdir/pr20267a.o tmpdir/libpr20267b.a" "" \
- {dummy.c} "pr20267b" "pass.out" "-flto -O2 -fcommon" "c"] \
[list "Run pr22502" \
"-O2 -flto tmpdir/pr22502a.o tmpdir/pr22502b.o" "" \
{dummy.c} "pr20267" "pass.out" "-flto -O2 -fcommon" "c"] \

41
SPECS/binutils.spec
Unescape View File

@ -2,7 +2,7 @@
Summary: A GNU collection of binary utilities
Name: binutils%{?_with_debug:-debug}
Version: 2.41
Release: 49%{?dist}
Release: 51%{?dist}
License: GPL-3.0-or-later AND (GPL-3.0-or-later WITH Bison-exception-2.2) AND (LGPL-2.0-or-later WITH GCC-exception-2.0) AND BSD-3-Clause AND GFDL-1.3-or-later AND GPL-2.0-or-later AND LGPL-2.1-or-later AND LGPL-2.0-or-later
URL: https://sourceware.org/binutils
@ -348,14 +348,31 @@ Patch41: binutils-aarch64-RELR.patch
# Lifetime: Fixed in 2.43
Patch42: binutils-Intel-APX-part-1-supplimental.patch
# Purpose: Add support for the arch14 (z16) and arch15 extensions to the
# s390 architecture.
# Lifetime: Fixed in 2.43
Patch43: binutils-s390-arch15-part-01.patch
Patch44: binutils-s390-arch15-part-02.patch
Patch45: binutils-s390-arch15-part-03.patch
Patch46: binutils-s390-arch15-part-04.patch
Patch47: binutils-s390-arch15-part-05.patch
Patch48: binutils-s390-arch15-part-06.patch
Patch49: binutils-s390-arch15-part-07.patch
Patch50: binutils-s390-arch15-part-08.patch
Patch51: binutils-s390-arch15-part-09.patch
Patch52: binutils-s390-arch15-part-10.patch
Patch53: binutils-s390-arch15-part-11.patch
Patch54: binutils-s390-arch15-part-12.patch
Patch55: binutils-s390-arch15-part-13.patch
Patch56: binutils-s390-arch15-part-14.patch
Patch57: binutils-s390-arch15-part-15.patch
#----------------------------------------------------------------------------
# Purpose: Workaround for an unresolved bug in ppc gcc
# which generates bad code in the linker. cf RHEL-49348
# Lifetime: TEMPORARY
Patch88: bin.ppc64.gcc.patch
# Purpose: Suppress the assembler's comment test as it fails - intermitantly - for RHEL-10
# Lifetime: TEMPORARY
# Patch98: binutils-suppress-gas-comment-test.patch
Patch98: bin.ppc64.gcc.patch
# Purpose: Suppress the x86 linker's p_align-1 tests due to kernel bug on CentOS-10
# Lifetime: TEMPORARY
@ -667,6 +684,7 @@ compute_global_configuration()
--enable-ld \
--enable-plugins \
--enable-64-bit-bfd \
--enable-default-hash-style=gnu \
--with-bugurl=%{dist_bug_report_url}"
%if %{without bootstrap}
@ -1390,9 +1408,14 @@ exit 0
#----------------------------------------------------------------------------
%changelog
* Tue Oct 29 2024 Troy Dawson <tdawson@redhat.com> - 2.41-49
- Bump release for October 2024 mass rebuild:
Resolves: RHEL-64018
* Mon Dec 02 2024 Nick Clifton <nickc@redhat.com> - 2.41-51
- Fix AArch64 linker testsuite problems.
* Mon Nov 18 2024 Nick Clifton <nickc@redhat.com> - 2.41-50
- Extend support for the arch14 and arch15 extensions to the s390 architecture. (RHEL-56896)
* Tue Nov 12 2024 Nick Clifton <nickc@redhat.com> - 2.41-49
- Add support for the arch14 and arch15 extensions to the s390 architecture. (RHEL-56896)
* Thu Aug 08 2024 Nick Clifton <nickc@redhat.com> - 2.41-48
- Restore LTO use when building binutils. (RHEL-53215)

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