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174 lines
8.0 KiB
174 lines
8.0 KiB
2 months ago
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From b8b60e2d0cb0ab1f235f082dbb8a4e8bc43aadf6 Mon Sep 17 00:00:00 2001
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From: Jens Remus <jremus@linux.ibm.com>
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Date: Thu, 12 Sep 2024 15:06:06 +0200
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Subject: [PATCH] s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints
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Commit: 69371b2a1567
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This leverages commit ("s390: Simplify (dis)assembly of insn operands
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with const bits") to relax the operand constraints of the immediate
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operand that contains the constant Z- or T-bit of the following extended
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mnemonics:
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risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
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Previously those instructions were the only ones where the assembler
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on s390 restricted the specification of the subject I3/I4 operand values
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exactly according to their specification to an unsigned 6- or 5-bit
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unsigned integer. For any other instructions the assembler allows to
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specify any operand value allowed by the instruction format, regardless
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of whether the instruction specification is more restrictive.
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Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
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with the constant operand bits being ORed during assembly.
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Relax the instructions subject significant operand bit masks to only
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consider the Z/T-bit as significant, so that the instructions get
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disassembled as their *z or *t flavor regardless of whether any reserved
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bits are set in addition to the Z/T-bit.
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Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
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the T-bit in operand I3, as they otherwise get disassembled as their
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rnsbgt, rosbgt, and rxsbgt counterpart.
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This aligns GNU Assembler to LLVM Assembler.
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opcodes/
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* s390-opc.c (U6_18, U5_27, U6_26): Remove.
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(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
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as INSTR_RIE_RRUUU while retaining insn fmt mask.
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(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
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Z/T-bit of I3/I4 operand as significant.
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gas/testsuite/
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* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.
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Reported-by: Dominik Steenken <dost@de.ibm.com>
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Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
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Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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---
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gas/testsuite/gas/s390/zarch-z10.d | 12 ++++++------
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gas/testsuite/gas/s390/zarch-z10.s | 12 ++++++------
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opcodes/s390-opc.c | 24 +++++++++---------------
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3 files changed, 21 insertions(+), 27 deletions(-)
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diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
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index 4a051533f93..beb057878d6 100644
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--- a/gas/testsuite/gas/s390/zarch-z10.d
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+++ b/gas/testsuite/gas/s390/zarch-z10.d
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@@ -359,20 +359,20 @@ Disassembly of section .text:
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.*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000
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.*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
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*([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
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-.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
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-.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220
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+.*: ec 67 6e dc e6 54 [ ]*rnsbg %r6,%r7,110,220,230
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+.*: ec 67 6e dc 00 54 [ ]*rnsbg %r6,%r7,110,220
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.*: ec 67 92 dc e6 54 [ ]*rnsbgt %r6,%r7,18,220,230
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.*: ec 67 92 dc 00 54 [ ]*rnsbgt %r6,%r7,18,220
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.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38
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.*: ec 67 92 1c 00 54 [ ]*rnsbgt %r6,%r7,18,28
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-.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
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-.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220
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+.*: ec 67 6e dc e6 57 [ ]*rxsbg %r6,%r7,110,220,230
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+.*: ec 67 6e dc 00 57 [ ]*rxsbg %r6,%r7,110,220
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.*: ec 67 92 dc e6 57 [ ]*rxsbgt %r6,%r7,18,220,230
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.*: ec 67 92 dc 00 57 [ ]*rxsbgt %r6,%r7,18,220
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.*: ec 67 92 1c 26 57 [ ]*rxsbgt %r6,%r7,18,28,38
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.*: ec 67 92 1c 00 57 [ ]*rxsbgt %r6,%r7,18,28
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-.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
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-.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220
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+.*: ec 67 6e dc e6 56 [ ]*rosbg %r6,%r7,110,220,230
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+.*: ec 67 6e dc 00 56 [ ]*rosbg %r6,%r7,110,220
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.*: ec 67 92 dc e6 56 [ ]*rosbgt %r6,%r7,18,220,230
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.*: ec 67 92 dc 00 56 [ ]*rosbgt %r6,%r7,18,220
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.*: ec 67 92 1c 26 56 [ ]*rosbgt %r6,%r7,18,28,38
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diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s
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index 45bb8944793..a6245888c4c 100644
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--- a/gas/testsuite/gas/s390/zarch-z10.s
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+++ b/gas/testsuite/gas/s390/zarch-z10.s
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@@ -353,20 +353,20 @@ foo:
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msgfi %r6,-100000
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pfd 10,5555(%r6,%r7)
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pfdrl 10,.
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- rnsbg %r6,%r7,210,220,230
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- rnsbg %r6,%r7,210,220
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+ rnsbg %r6,%r7,110,220,230
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+ rnsbg %r6,%r7,110,220
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rnsbg %r6,%r7,146,220,230
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rnsbg %r6,%r7,146,220
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rnsbgt %r6,%r7,18,28,38
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rnsbgt %r6,%r7,18,28
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- rxsbg %r6,%r7,210,220,230
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- rxsbg %r6,%r7,210,220
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+ rxsbg %r6,%r7,110,220,230
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+ rxsbg %r6,%r7,110,220
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rxsbg %r6,%r7,146,220,230
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rxsbg %r6,%r7,146,220
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rxsbgt %r6,%r7,18,28,38
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rxsbgt %r6,%r7,18,28
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- rosbg %r6,%r7,210,220,230
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- rosbg %r6,%r7,210,220
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+ rosbg %r6,%r7,110,220,230
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+ rosbg %r6,%r7,110,220
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rosbg %r6,%r7,146,220,230
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rosbg %r6,%r7,146,220
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rosbgt %r6,%r7,18,28,38
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diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
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index 987004d7b07..fe0299aa4e5 100644
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--- a/opcodes/s390-opc.c
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+++ b/opcodes/s390-opc.c
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@@ -216,15 +216,9 @@ const struct s390_operand s390_operands[] =
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{ 4, 36, 0 },
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#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
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{ 8, 8, 0 },
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-#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */
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- { 6, 18, 0 },
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-#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */
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+#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
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{ 8, 16, 0 },
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-#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */
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- { 5, 27, 0 },
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-#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */
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- { 6, 26, 0 },
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-#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
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+#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */
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{ 8, 24, 0 },
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#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */
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{ 8, 28, 0 },
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@@ -288,7 +282,7 @@ unused_s390_operands_static_asserts (void)
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p - pc relative
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r - general purpose register
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re - gpr extended operand, a valid general purpose register pair
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- u - unsigned integer, 4, 6, 8, 16 or 32 bit
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+ u - unsigned integer, 4, 8, 16 or 32 bit
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m - mode field, 4 bit
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0 - operand skipped.
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The order of the letters reflects the layout of the format in
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@@ -324,9 +318,9 @@ unused_s390_operands_static_asserts (void)
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#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
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#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
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#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
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-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */
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-#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */
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-#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */
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+#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */
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+#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */
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+#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */
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#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
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#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
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#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
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@@ -551,9 +545,9 @@ unused_s390_operands_static_asserts (void)
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#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
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#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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-#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
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-#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff }
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-#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff }
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+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
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+#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
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+#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff }
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#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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--
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2.47.0
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