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165 lines
6.6 KiB
165 lines
6.6 KiB
3 months ago
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From 83bb32c25472b500738a54ac8f2ad0f5c496acf1 Mon Sep 17 00:00:00 2001
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From: Isaku Yamahata <isaku.yamahata@linux.intel.com>
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Date: Wed, 20 Mar 2024 03:39:14 -0500
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Subject: [PATCH 009/100] q35: Introduce smm_ranges property for q35-pci-host
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 245: SEV-SNP support
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RH-Jira: RHEL-39544
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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RH-Acked-by: Bandan Das <bdas@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Commit: [9/91] 931156772bfc2085e7241eecc56cf6eca3dac1fd (bonzini/rhel-qemu-kvm)
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Add a q35 property to check whether or not SMM ranges, e.g. SMRAM, TSEG,
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etc... exist for the target platform. TDX doesn't support SMM and doesn't
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play nice with QEMU modifying related guest memory ranges.
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Signed-off-by: Isaku Yamahata <isaku.yamahata@linux.intel.com>
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Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
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Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
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Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Signed-off-by: Michael Roth <michael.roth@amd.com>
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Message-ID: <20240320083945.991426-19-michael.roth@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit b07bf7b73fd02d24a7baa64a580f4974b86bbc86)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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hw/i386/pc_q35.c | 2 ++
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hw/pci-host/q35.c | 42 +++++++++++++++++++++++++++------------
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include/hw/i386/pc.h | 1 +
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include/hw/pci-host/q35.h | 1 +
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4 files changed, 33 insertions(+), 13 deletions(-)
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diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
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index 9adcdadce8..dedc86eec9 100644
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--- a/hw/i386/pc_q35.c
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+++ b/hw/i386/pc_q35.c
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@@ -219,6 +219,8 @@ static void pc_q35_init(MachineState *machine)
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x86ms->above_4g_mem_size, NULL);
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object_property_set_bool(phb, PCI_HOST_BYPASS_IOMMU,
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pcms->default_bus_bypass_iommu, NULL);
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+ object_property_set_bool(phb, PCI_HOST_PROP_SMM_RANGES,
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+ x86_machine_is_smm_enabled(x86ms), NULL);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
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/* pci */
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diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
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index 98d4a7c253..0b6cbaed7e 100644
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--- a/hw/pci-host/q35.c
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+++ b/hw/pci-host/q35.c
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@@ -179,6 +179,8 @@ static Property q35_host_props[] = {
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mch.below_4g_mem_size, 0),
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DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
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mch.above_4g_mem_size, 0),
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+ DEFINE_PROP_BOOL(PCI_HOST_PROP_SMM_RANGES, Q35PCIHost,
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+ mch.has_smm_ranges, true),
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DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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@@ -214,6 +216,7 @@ static void q35_host_initfn(Object *obj)
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/* mch's object_initialize resets the default value, set it again */
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qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE,
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Q35_PCI_HOST_HOLE64_SIZE_DEFAULT);
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+
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
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q35_host_get_pci_hole_start,
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NULL, NULL, NULL);
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@@ -476,6 +479,10 @@ static void mch_write_config(PCIDevice *d,
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mch_update_pciexbar(mch);
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}
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+ if (!mch->has_smm_ranges) {
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+ return;
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+ }
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+
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if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
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MCH_HOST_BRIDGE_SMRAM_SIZE)) {
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mch_update_smram(mch);
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@@ -494,10 +501,13 @@ static void mch_write_config(PCIDevice *d,
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static void mch_update(MCHPCIState *mch)
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{
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mch_update_pciexbar(mch);
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+
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mch_update_pam(mch);
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- mch_update_smram(mch);
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- mch_update_ext_tseg_mbytes(mch);
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- mch_update_smbase_smram(mch);
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+ if (mch->has_smm_ranges) {
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+ mch_update_smram(mch);
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+ mch_update_ext_tseg_mbytes(mch);
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+ mch_update_smbase_smram(mch);
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+ }
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/*
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* pci hole goes from end-of-low-ram to io-apic.
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@@ -538,18 +548,20 @@ static void mch_reset(DeviceState *qdev)
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pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
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- d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
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- d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
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- d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
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- d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
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+ if (mch->has_smm_ranges) {
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+ d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
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+ d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
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+ d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
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+ d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
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- if (mch->ext_tseg_mbytes > 0) {
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- pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
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- MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
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- }
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+ if (mch->ext_tseg_mbytes > 0) {
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+ pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
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+ MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
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+ }
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- d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0;
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- d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff;
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+ d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0;
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+ d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff;
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+ }
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mch_update(mch);
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}
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@@ -578,6 +590,10 @@ static void mch_realize(PCIDevice *d, Error **errp)
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PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
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}
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+ if (!mch->has_smm_ranges) {
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+ return;
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+ }
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+
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/* if *disabled* show SMRAM to all CPUs */
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memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
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mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE,
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diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
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index 87420783ab..467e7fb52f 100644
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--- a/include/hw/i386/pc.h
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+++ b/include/hw/i386/pc.h
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@@ -164,6 +164,7 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
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#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
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#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
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#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
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+#define PCI_HOST_PROP_SMM_RANGES "smm-ranges"
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void pc_pci_as_mapping_init(MemoryRegion *system_memory,
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diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
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index bafcbe6752..22fadfa3ed 100644
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--- a/include/hw/pci-host/q35.h
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+++ b/include/hw/pci-host/q35.h
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@@ -50,6 +50,7 @@ struct MCHPCIState {
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MemoryRegion tseg_blackhole, tseg_window;
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MemoryRegion smbase_blackhole, smbase_window;
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bool has_smram_at_smbase;
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+ bool has_smm_ranges;
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Range pci_hole;
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uint64_t below_4g_mem_size;
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uint64_t above_4g_mem_size;
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--
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2.39.3
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