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84 lines
2.9 KiB
84 lines
2.9 KiB
2 years ago
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From 416de21d11540a927cceb533bf54ce28ffa15ad6 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Thu, 24 Mar 2022 09:21:41 +0100
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Subject: [PATCH 2/3] target/i386: properly reset TSC on reset
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 172: target/i386: properly reset TSC on reset
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RH-Commit: [1/1] 7008bc5d02ad0a2d8b78259459d22d8f0986c989
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RH-Bugzilla: 2070417
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RH-Acked-by: Marcelo Tosatti <None>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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Some versions of Windows hang on reboot if their TSC value is greater
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than 2^54. The calibration of the Hyper-V reference time overflows
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and fails; as a result the processors' clock sources are out of sync.
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The issue is that the TSC _should_ be reset to 0 on CPU reset and
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QEMU tries to do that. However, KVM special cases writing 0 to the
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TSC and thinks that QEMU is trying to hot-plug a CPU, which is
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correct the first time through but not later. Thwart this valiant
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effort and reset the TSC to 1 instead, but only if the CPU has been
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run once.
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For this to work, env->tsc has to be moved to the part of CPUArchState
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that is not zeroed at the beginning of x86_cpu_reset.
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Reported-by: Vadim Rozenfeld <vrozenfe@redhat.com>
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Supersedes: <20220324082346.72180-1-pbonzini@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 5286c3662294119dc2dd1e9296757337211451f6)
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---
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target/i386/cpu.c | 13 +++++++++++++
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target/i386/cpu.h | 2 +-
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2 files changed, 14 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 6e25d13339..dd6935b1dd 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5871,6 +5871,19 @@ static void x86_cpu_reset(DeviceState *dev)
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env->xstate_bv = 0;
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env->pat = 0x0007040600070406ULL;
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+
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+ if (kvm_enabled()) {
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+ /*
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+ * KVM handles TSC = 0 specially and thinks we are hot-plugging
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+ * a new CPU, use 1 instead to force a reset.
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+ */
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+ if (env->tsc != 0) {
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+ env->tsc = 1;
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+ }
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+ } else {
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+ env->tsc = 0;
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+ }
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+
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env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
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if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
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env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 04f2b790c9..c6a6c871f1 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -1510,7 +1510,6 @@ typedef struct CPUX86State {
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target_ulong kernelgsbase;
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#endif
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- uint64_t tsc;
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uint64_t tsc_adjust;
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uint64_t tsc_deadline;
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uint64_t tsc_aux;
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@@ -1660,6 +1659,7 @@ typedef struct CPUX86State {
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int64_t tsc_khz;
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int64_t user_tsc_khz; /* for sanity check only */
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uint64_t apic_bus_freq;
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+ uint64_t tsc;
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#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
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void *xsave_buf;
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uint32_t xsave_buf_len;
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--
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2.35.1
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