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89 lines
3.1 KiB
89 lines
3.1 KiB
9 months ago
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From 6eae12166341c236da023e5117b64b842ae72083 Mon Sep 17 00:00:00 2001
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From: Jing Liu <jing2.liu@intel.com>
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Date: Wed, 16 Feb 2022 22:04:27 -0800
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Subject: [PATCH 05/24] x86: Fix the 64-byte boundary enumeration for extended
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state
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RH-Author: Paul Lai <plai@redhat.com>
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RH-MergeRequest: 176: Enable KVM AMX support
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RH-Commit: [5/13] 64fc93e3b0ad0fc56da9d71b33d9eefd3cbba1d7
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RH-Bugzilla: 1916415
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
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indicate whether the extended state component locates
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on the next 64-byte boundary following the preceding state
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component when the compacted format of an XSAVE area is
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used.
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Right now, they are all zero because no supported component
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needed the bit to be set, but the upcoming AMX feature will
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use it. Fix the subleaves value according to KVM's supported
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cpuid.
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Signed-off-by: Jing Liu <jing2.liu@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-2-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 131266b7565bd437127bd231563572696bb27235)
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Signed-off-by: Paul Lai <plai@redhat.com>
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---
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target/i386/cpu.c | 1 +
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target/i386/cpu.h | 6 ++++++
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target/i386/kvm/kvm-cpu.c | 1 +
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3 files changed, 8 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index dd6935b1dd..f44fad3a2a 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5495,6 +5495,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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const ExtSaveArea *esa = &x86_ext_save_areas[count];
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*eax = esa->size;
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*ebx = esa->offset;
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+ *ecx = esa->ecx & ESA_FEATURE_ALIGN64_MASK;
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}
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}
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break;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index c6a6c871f1..5d9702a991 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -548,6 +548,11 @@ typedef enum X86Seg {
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#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
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#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
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+#define ESA_FEATURE_ALIGN64_BIT 1
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+
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+#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
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+
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+
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/* CPUID feature words */
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typedef enum FeatureWord {
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FEAT_1_EDX, /* CPUID[1].EDX */
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@@ -1354,6 +1359,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
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typedef struct ExtSaveArea {
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uint32_t feature, bits;
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uint32_t offset, size;
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+ uint32_t ecx;
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} ExtSaveArea;
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#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1)
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diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
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index 7b004065ae..86ef7b2712 100644
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--- a/target/i386/kvm/kvm-cpu.c
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+++ b/target/i386/kvm/kvm-cpu.c
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@@ -104,6 +104,7 @@ static void kvm_cpu_xsave_init(void)
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if (sz != 0) {
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assert(esa->size == sz);
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esa->offset = kvm_arch_get_supported_cpuid(s, 0xd, i, R_EBX);
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+ esa->ecx = kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX);
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}
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}
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}
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--
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2.35.3
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