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69 lines
2.6 KiB
69 lines
2.6 KiB
1 month ago
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From fe60f8d47b6e14f17dd6c06b03bd00e6bcdbeefb Mon Sep 17 00:00:00 2001
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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
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Date: Wed, 20 Mar 2024 17:31:38 +0800
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Subject: [PATCH 005/100] target/i386: Introduce Icelake-Server-v7 to enable
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TSX
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 245: SEV-SNP support
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RH-Jira: RHEL-39544
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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RH-Acked-by: Bandan Das <bdas@redhat.com>
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Commit: [5/91] 66d865899e0d510b6c86763422d6b28b904b208a (bonzini/rhel-qemu-kvm)
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When start L2 guest with both L1/L2 using Icelake-Server-v3 or above,
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QEMU reports below warning:
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"warning: host doesn't support requested feature: MSR(10AH).taa-no [bit 8]"
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Reason is QEMU Icelake-Server-v3 has TSX feature disabled but enables taa-no
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bit. It's meaningless that TSX isn't supported but still claim TSX is secure.
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So L1 KVM doesn't expose taa-no to L2 if TSX is unsupported, then starting L2
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triggers the warning.
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Fix it by introducing a new version Icelake-Server-v7 which has both TSX
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and taa-no features. Then guest can use TSX securely when it see taa-no.
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This matches the production Icelake which supports TSX and isn't susceptible
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to TSX Async Abort (TAA) vulnerabilities, a.k.a, taa-no.
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Ideally, TSX should have being enabled together with taa-no since v3, but for
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compatibility, we'd better to add v7 to enable it.
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Fixes: d965dc35592d ("target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model")
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Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
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Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
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Message-ID: <20240320093138.80267-2-zhenzhong.duan@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit c895fa54e3060c5ac6f3888dce96c9b78626072b)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index a7f71422ea..0aa88d9b48 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -3840,6 +3840,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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},
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},
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+ {
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+ .version = 7,
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+ .note = "TSX, taa-no",
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+ .props = (PropValue[]) {
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+ /* Restore TSX features removed by -v2 above */
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+ { "hle", "on" },
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+ { "rtm", "on" },
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+ { /* end of list */ }
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+ },
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+ },
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{ /* end of list */ }
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}
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},
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--
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2.39.3
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